Emulation device for converting magnetic disc memory mode signal from computer into semiconductor memory access mode signal for semiconductor memory

• US 4,896,262 A
• Filed: 02/22/1985
• Issued: 01/23/1990
• Est. Priority Date: 02/24/1984
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Meidensha
• Original Assignee: Kabushiki Kaisha Meidensha
• Inventors: Shinozaki, Michio, Miyajima, Naoto, Wayama, Yukio, Yashima, Kazunari
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Chan, Emily Y.
• Application Number:
  US06/704,520
• Time in Patent Office: 1,796 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/65
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system

Abstract

A semiconductor backing storage device is connected to a computer system accessible only in magnetic disc access mode for improvement in access time. In transferring information data between the computers and the semiconductor backing storage device, access control command signals peculiar to magnetic disc access mode are all disregarded and address data peculiar to magnetic disc access mode are converted into those necessary for semiconductor memory mode in writing or reading information data. To further decrease access time, one-word buffers are provided for a semiconductor backing storage controller and the backing storage device, so that the preceding data are transferred from the buffers while the current data are transferred to the buffers after necessary processing. The semiconductor backing storage memory is also usable for a multicomputer system by providing cross-call function for the semiconductor backing storage controller.

Claims

1. A data processing system including an apparatus for auxiliary storing data transferred from a computer via a computer bus, said apparatus comprising:

(a) first means, including a semiconductor memory and memory bus;

(b) second means interposed between the computer bus and the memory bus for converting a first access mode signal for the magnetic disc memory from the computer into a second access mode signal for the semiconductor memory and controlling data transfer between a central processing unit (CPU) of the computer and the first means, the CPU transmitting and receiving address data to and from the first means, in transferring information data between the computer and the semiconductor memory, the second means omitting data access control command signals from the CPU to the semiconductor memory, while providing access control command signals from the CPU unique to the magnetic disc access mode and converting the address data to and from the CPU unique to the magnetic disc access mode into address data for the semiconductor memory access mode, and omitted data access control command signals being DISC SELECT DRIVE, PACK ACKNOWLEDGE, DRIVE CLEAR, UNLOAD, START SPINDLE MOTOR, RECALIBRATE, OFF SET, and WRITE HEADER, the other non-omitted data access control command signals being SEEK, READ, WRITE, READ HEADER and WRITE CHECK, the prepared data access control command being HEADER, the addressed data unique to the magnetic disc access mode being CYLINDER, TRACK, HEAD, and SECTOR, and the address data unique to the semiconductor access mode being POW ADDRESS STROBE and COLUMN ADDRESS STROBE.

2. An apparatus as set forth in claim 1, wherein a plurality of said semiconductor memories are connected in parallel to said computer bus.

3. An apparatus for auxiliary storing data transferred from a computer via a computer bus, comprising:

(a) first means including a semiconductor memory and a storage bus; and

(b) second means interposed between the computer bus and the storage bus for converting an access mode signal from the computer into a second access mode signal for the semiconductor memory and controlling data transfer between a central processing unit (CPU) of the computer and the first means in response to the converted access mode signal, wherein said second means comprises;

(c) computer bus driver/receiver means connected to the computer bus for receiving from said CPU said data access control command signals, address data and information data prepared in magnetic disc access mode and transmitting to said CPU control signals of direct memory access, interrupt signals, data access control command signals, address data and information data prepared in said magnetic disc access mode;

(d) storage bus driver/receiver means connected to the storage bus for receiving information data read from said semiconductor memory and transmitting to said semiconductor memory data access control command signals of READ, WRITE, WRITE CHECK, and address data necessary for semiconductor memory access and information data to be written in said semiconductor memory;

(e) a condition code multiplexer means connected to said computer bus driver/receiver means for poll-scanning said computer bus driver/receiver means to check sequentially whether the computer is accessing said semiconductor memory and for outputting said data access control command signals;

(f) microprogram sequencer means connected to said condition code multiplexer means for generating microprogram address designation signals in sequence in response to the data access control command signals and clock pulse signals generated by a system clock;

(g) read only memory means connected to said microprogram sequencer for outputting microprogram instructions in response to the microprogram address designation signals;

(h) register means connected to said read only memory means, said microprogram sequencer means and said condition code multiplexer means for inputting the microprogram from said read only memory there into as microinstructions in response to said clock pulse signals and for outputting succeeding sequencer addresses and instruction signals to said microprogram sequencer means and a multiplexer control signal to said condition code multiplexer means;

(i) random access memory means connected to said computer bus receiver/driver means, said storage bus receiver/driver means and said register means for temporarily storing addresses, data, information data, data access control command signals, etc.; and

(j) microprocessor means connected to said computer bus receiver/driver means, said storage bus receiver/driver means, said random access memory means, and said register means for writing/reading information data in or out of said semiconductor memory in response to command signals received through said computer bus driver/receiver means in accordance with the microprogram instructions transferred from said read-only memory means to said register means, said microprocessor means including means for analyzing said data access control command signals, omitting data access control command signals peculiar to said magnetic disc access mode, means for selecting data access control command signals of READ, WRITE, READ HEADER and WRITE CHECK necessary for transferring information data between the computer and said semiconductor memory, means for reading information data from said semiconductor memory, means for preparing a magnetic disc header in accordance with the microprogram instructions and converting address data peculiar to the semiconductor memory access mode into address data necessary for the magnetic disc access mode in accordance with the microprogram, and means for writing information data in said semiconductor memory, and converting said address data peculiar to the magnetic disc access mode to address data necessary for the semiconductor memory access mode in accordance with the microprogram instructions, so that information data may be transferred between the computer and said semiconductor memory.

4. An apparatus as set forth in claim 3, which further comprises an error correction code control means connected to a data bus disposed between said computer bus driver/receiver and said storage bus driver/receiver said error correction control means including means for adding an automatic error correction code to information data in writing information data to said semiconductor memory, and means for checking the added error correction code and automatically correcting checked information data in case of presence of error in reading information data from said semiconductor memory.

8. An apparatus as set forth in claim 3, wherein said computer bus driver/receiver means and said storage bus driver/receiver means both comprise therein one-word buffer means, respectively, for temporarily storing information data in transferring information data between the computer and said semiconductor memory in order that a succeeding information data is transferred to said buffer means while the current information data are transferred from said buffer means.

10. An apparatus as set forth in claim 8, wherein each one-word buffer means includes a plurality of one-bit buffers each of which comprises:

(a) a first flip-flop means for latching information data on a first bus line in response to an internal buffer signal and outputting the latched data onto a second bus line in response to a write command signal;

(b) a second flip-flop means connected in parallel with said first flip-flop means for latching data on the second bus line in response to a read command signal and outputting the latched data onto the first bus line in response to an inversed read command signal.

5. An apparatus for auxiliary storing data transferred from a computer via a computer bus, comprising:

(a) first means including a semiconductor memory and a storage bus;

(b) second means interposed between the computer bus and the memory bus for converting a first access mode signal from the computer into a second access mode signal for the semiconductor memory and controlling data transfer between a central processing unit (CPU) of the computer and the first means in response to the converted access mode signal, wherein the semiconductor memory comprises;

(c) semiconductor storage array means for storing said information data; and

(d) semiconductor array control means comprising;

(1) address control means connected between said second means and said semiconductor storage array means for receiving address data from said storage control means, for generating signals to select areas to be allocated to said storage array means in response to the address data, and for outputting address data and address selection signals together;

(2) error correction code control means connected between said second means and said semiconductor storage array means, said error correction code control means including means for receiving information data to be read out of or written in said semiconductor memory, means for adding a word error correction code to said information data, means for checking said added word correction code in reading the information data, and means for automatically correcting said read information data in case of presence of error;

(3) control signal generating means connected between said second means and said storage array means for generating control signals that are supplied to said semiconductor storage array and are necessary for transferring information data between said second means and said semiconductor storage array means;

(4) sequence control means connected to said address control means, said error correction code control means and said control signal generating means for generating control signals to sequentially and timingly control said address control means, said error correction code control means and said control signal generating means.

6. An apparatus as set forth in claim 5, wherein control signals generated by said control signal generating means include row address strobe (RAS), column address strobe (CAS), write-enable (WE), read-enable (RE), and drive enable (DREN) in the case where said semiconductor storage array means is a dynamic random access memory.

7. An apparatus as set forth in claim 5, wherein said semiconductor storage array means comprises:

(a) semiconductor storage element means storing said information data;

(b) address selection logic means connected between said address control means and said storage element means for generating address data signals to said semiconductor storage element means in response to address data signals from said address control means;

(c) address matrix selection control means connected between said control signal generating means and said semiconductor storage element means and to said address selection logic means for generating row address selection signals and column address selection signals to said semiconductor storage element means in response to row address signals and column address signals from said control signal generating means and the address data signals from said address selection logic means;

(d) write enable signal generating means connected between said control signal generating means and said semiconductor storage element means and to said address selection logic means for outputting a write control signal WR to said storage element means in response to a write enable signal from said control signal generating means and address data signals from said address selection logic means;

(e) write buffer means connected between said error correction code control means and said semiconductor storage element means for writing said information data received from said error correction control means in said semiconductor storage element means in response to the write control signal WR from said write enable signal generating means; and

(f) read buffer means connected between said control signal generating means and said error correction code control means, and said semiconductor storage element means and to said address selection logic means for reading information data from said semiconductor storage element means in response to a data read signal from said control signal generating means and the address data signal from said address selection logic means, said information data being transferred from said read buffer means to said error correction code control means.

9. An apparatus as set forth in claim 5, wherein said error correction code control means comprises therein one-word buffer means for temporarily storing information data in transferring information data between said second means and said semiconductor memory in order that a succeeding information data are EEC processed and transferred to said buffer means while current information data are transferred from said buffer means.

11. An apparatus as set forth in claim 9, wherein each one-word buffer means includes a plurality of one-bit buffers each of which comprises:

(a) a first flip-flop means for latching information data on a first bus line in response to an internal buffer signal and outputting the latched data onto a second bus line in response to a write command signal; and

(b) a second flip-flop means connected in parallel with said first flip-flop means for latching data on the second bus line in response to a read command signal and outputting the latched data onto the first bus line in response to an inversed read command signal.

12. An apparatus as set forth in claim 5, wherein said semiconductor memory is shared by plural computers via plural second means, said semiconductor memory comprises semiconductor array control means connected between said plural second means and said semiconductor storage array means, said semiconductor array control means further comprises:

(a) a first data logic port means connected between a first of said second means, and said address control means and said error code correction control means for temporarily storing addresses and information data supplied from said first of said second means;

(b) a second data logic port means connected between a second of said second means, and said address control means and said error code correction control means for temporarily storing addresses and information data supplied from said second of said second means;

(c) a control logic port means connected to said first and second of said second means for storing and outputting control signals of READ, WRITE and WRITE CHECK generated separately from said first and second of said second means; and

(d) cross-call control means connected to said first and second data logic port means, said control logic port means and said sequence control means said cross-call control means including means for designating one of said first and second data logic port means in response to the control signals outputted from said control logic port means under priority or a first-in first-out condition, means for defining specific addresses in said semiconductor storage array means for information data outputted from said designated data logic port means, and means for interlocking address and information data both stored in one of said first and second data logic ports in case both said first and second of said second means generate access signals to said shared semiconductor memory simultaneously.