Test interface circuit which generates different interface control signals for different target computers responding to control signals from host computer

• US 4,899,306 A
• Filed: 08/26/1985
• Issued: 02/06/1990
• Est. Priority Date: 08/26/1985
• Status: Expired due to Fees

• Current Assignee: Telephone Laboratories Incorporated
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Greer, Steven C.
• Primary Examiner(s): Lee, Thomas
• Application Number:
  US06/769,138
• Time in Patent Office: 1,625 Days
• Field of Search: 371/15, 371/20, 371/16, 324/73 R, 324/73 AT, 364/200 MS File, 364/900 MS File, 364/480, 364/579, 364/580
• US Class Current: 710/64
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test

Abstract

A general purpose computer test interface is used to test various types of computers having differing input/output characteristics. The interface comprises a control unit which is responsive to messages from a controlling host computer to generate a unique set of type control signals for each computer type to be tested. Interfce control logic circuits combine the type control signals with bus control signals from a target computer under test to adapt the interface for communication with each of the different types of targets defined by the type control signals.

Claims

1. An adaptable test interface for use with a host computer and a plurality of target computers of different types having differing input/output characteristics comprising:

memory means;

first control means, connected to said memory means, responsive to control signals from said host computer to write test data received from said host computer into and read target output data from said memory means and to generate a unique set of interpretation control signals for each computer type to be tested;

interconnecting means for connecting said first control means to said host computer;

second control means, connected to said first control means, responsive to said interpretation controll signals and control signals from a target computer to be tested for generating interface control signals; and

address decoder means, connected to said second control means, responsive to said interface control signals and address signals from said target computer to generate memory control signals;

said memory means, connected to said address decoder means, responsive to said memory control signals to access memory locations defined by said address signals from said target computer and selectively transmit said test data to and store said target output data from said target computer;

whereby a target computer obtains from the memory means test data supplied by the host computer and returns target output data to the memory means for examination by the host computer.

2. An adaptable test interface for use in testing a plurality of computers of different types having differing input/output characteristics, comprising:

data storage means;

first control means, connected to said data storage means, responsive to control signals from a host test computer to generate a unique set of interpretation control signals for each computer type to be tested and first data storage access signals for writing test data received from said host test computer into and reading target output data from said data storage means;

interconnecting means for connecting said first control means to said host test computer;

second control means, connected to said first control means, responsive to said interpretation control signals and control signals from a target computer to be tested for generating interface control signals; and

address decoder means, connected to said second control means, responsive to said interface control signals and address signals from said target computer to generate second data storage access signals;

said data storage means, connected to said address decoder means, respnsive to said first data storage access signals to store said test data received from and transmit said target output data to said first control means and responsive to said second data storage access signals to access locations of said data storage means defined by said address signals from said target computer and to stare said target output data received from and transmit said test data to said target computer;

whereby a host test computer communicates with different types of target computers via said first control means and said data storage means.

3. An adaptable test interface in accordance with claim 2 wherein said first control means is further responsive to control signals from said host to transmit data defining an address range to said address decoder means and said address decoder means comprises comparator means for comparing a peripheral address from said target computer with said data defining a valid address range to generate said second data storage control signals.

4. A general purpose test interface circuit for testing a plurality of different types of processors, comprising:

interface memory means;

a control unit, connected to said interface memory means, responsive to control signals from a host computer for reading data from and writing into said interface memory means and for generating a unique set of processor type control signals for each different type of processor to be tested and data words defining valid target addresses for each type of processor to be tested;

interconnecting means for connecting said control unit to said host computer;

logic circuit means connected to said control unit for logically combining bus control signals received from a target processor to be tested and said processor type control signals into interface control signals corresponding to the type of target processor to be tested; and

address decoder means, connected to said control unit, responsive to address signals from said target processor and said data words defining valid target addresses to generate memory control signals;

said interface memory means, connected to said logic circuit means and said address decoder means responsive to said memory control signals and said interface control signals for selectively storing and retrieving target processor data at memory locations defined by said address signals from said target processor.

5. An adaptable interface unit for use with a host computer which generates test control information for testing a plurality of different types of target processors having differing input/output characteristics, and a target processor to be tested, comprising:

data link connection means for connection to said host computer;

first control means connected to said data link connection means and responsive to said test control information for generating a unique set of processor type control signals for each type of processor to be tested;

memory means for storing data words of a word length equivalent to the length of the longest word expected from any of said target processors;

said first control means responsive to memory access control signals from said host computer to transfer data between said memory means and said host computer;

data bus means connected to said memory means and comprising a plurality of bus sections;

data buffer means for connection to said target processor, connected to said data bus means and responsive to buffer control signals to selectively transfer data words of varying word length between different types of target processors and predetermined sections of said bus means;

second control means connected to said buffer means and said first control means, and responsive to said processor type control signals and data transfer control signals generated by said target processor to generate said buffer control signals to control said data buffer means to selectively transfer data words of a length defined by said processor type control signals and said data transfer control signals between said target processor and predetermined sections of said data bus means.

6. An adaptable interface unit for use with a host computer which generates test control information for testing a plurality of different types of target processors having differing input/output characteristics, and a target processor to be tested, comprising:

data link connection means for connection to said host computer;

first control means connected to said data link connection means and responsive to said test control information for generating a unique set of processor type control signals for each type of processor to be tested;

memory means for storing data words of a word length equivalent to the length of the longest word expected from any of said target processors;

said first control means responsive to memory access control signals from said host computer to transfer data between said memory means and said host computer;

data bus means connected to said memory means and comprising a plurality of bus sections;

data buffer means for connection to said target processor, connected to said data bus means and responsive to buffer control signals to selectively transfer data words of varying word length between different types of target processors and predetermined sections of said bus means; and

second control means connected to said buffer means and said first control means, and responsive to said processor type control signals and data transfer control signals generated by said target processor to generate said buffer control signals to control said data buffer means to selectively transfer data words of a length defined by said processor type control signals and said data transfer control signals between said target processor and predetermined sections of said data bus means;

said memory means comprising a plurality of memory sections, each section corresponding to a section of said data bus means;

said second control means comprising memory control means connected to said memory means and said first control means and responsive to said processor type control signals and said data transfer control and address signals generated by said specific target processor to generate memory enable signals to selectively enable said memory sections to store data words of a length defined by said processor type control signals and said transfer control signals from said target processor, and means responsive to said memory enable signals to generate said buffer control signals to control said data buffer means to selectively transfer data words between said specific target processor and sections of said data bus corresponding to said memory sections defined by said memory enable signals.