Making a silicon-on-insulator transistor with selectable body node to source node connection

• US 4,906,587 A
• Filed: 07/29/1988
• Issued: 03/06/1990
• Est. Priority Date: 07/29/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Blake, Terence G. W.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US07/226,106
• Time in Patent Office: 585 Days
• Field of Search: 357/23.7, 357/23.5, 437/40, 437/41, 437/27, 437/83, 437/200, 437/84, 437/45
• US Class Current: 438/151
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Abstract

A silicon-on-insulator MOS transistor is disclosed which has contact regions on both the source and drain sides of the gate electrode for potentially making contact to the body node from either side. Each contact region is of the same conductivity type as the body node, (for example, a p-type region for an n-channel transistor), and may be formed by blocking all source/drain implants from the contact regions, so that the contact region remains substantially with the same doping concentration as that of the body region. A mask is provided prior to silicidation so that the contact regions on either side of the gate electrode are not connected by silicide to the adjacent source/drain doped regions. Once a side is selected to be the source of the transistor, ohmic connection is then made between the abutting source region and the contact region by way of contacts through an overlying interlevel dielectric and metallization. A second embodiment of the transistor is disclosed which provides such contact with reduction in the channel width, by allowing the lightly-doped drain extension of the source and drain to be present between the contact region and the gate electrode at the surface of the structure. A configuration of multiple transistors on a common mesa is also disclosed, where each one of the transistors has a contact region on both sides of its gate so that all of the contact regions on the mesa are connected through the body nodes of the transistors. A single body-to-source node connection can thus provide body node bias for all of the transistors on the mesa.

Claims

1. A method of fabricating a transistor in a semiconductor layer overlying an insulating film, comprising:

defining an active portion of said semiconductor layer of a first conductivity type;

forming a gate electrode over said active portion;

applying a first mask layer over said active portion to protect a first contact region on a first side of said gate electrode and a second contact region on a second side of said gate electrode;

doping regions of said active portion not protected by said first mask layer with dopant of a second conductivity type;

applying a second mask layer over said active portion to protect said first and second contact regions, and to protect portions of said doped regions adjacent to said first and second contact regions;

forming a silicide film over said doped regions not protected by said second mask layer;

forming an interlevel dielectric layer overall;

etching a contact via through said interlevel dielectric to contact said first contact region; and

forming a metal line in contact with said first contact region through said contact via.

2. The method of claim 1, wherein said contact via overlaps a boundary between said first contact region and the adjacent portion of said dope region.

3. The method of claim 1, wherein said contact via is disposed within said first contact region.

4. The method of claim 1, further comprising:

etching a second contact via through said interlevel dielectric layer to contact the doped region on said first side of said gate electrode;

and wherein said metal line is formed also in contact with said doped region through second contact via.

5. The method of claim 1, further comprising, after said step of doping said regions;

forming sidewall dielectric filaments on said first and second sides of said gate electrode;

applying a third mask layer over said active portion to protect said first and second contact regions

additionally doping first and second regions of said active portion not protected by said first mask layer with dopant of a second conductivity type, said additionally doping step resulting in heavier doping concentration than said first doping step.

6. A method of fabricating a transistor in a semiconductor layer overlying an insulating film, comprising:

defining an active portion of said semiconductor layer of a first conductivity type;

forming a gate electrode over said active portion;

applying a first mask layer over said active portion to protect a first contact region on a first side of said gate electrode and a second contact region on a second side of said gate electrode;

doping first and second regions of said active portion not protected by said first mask layer with dopant of a second conductivity type, said first and second doped regions disposed on said first and second sides of said gate electrode respectively;

applying a second mask layer over said active portion to protect said first and second contact regions, and to protect portions of said first and second doped regions adjacent to said first and second contact regions, respectively;

forming a silicide film over said first and second doped regions where not protected by said second mask layer;

forming an interlevel dielectric layer overall;

selecting either said first or said second doped regions as the source of the transistor;

etching a contact via through said interlevel dielectric to contact the selected doped region and to contact the contact region on the side of said selected doped region;

forming a metal line in contact with said selected doped region and the contact region through said contact vias.

7. The method of claim 6, wherein said contact via in contact with the contact region overlaps a boundary between said contact region and the adjacent portion of said doped region.

8. The method of claim 6, wherein said contact via in contact with the contact region is disposed within said first contact region.

9. The method of claim 6, further comprising, after said step of doping said regions;

forming sidewall dielectric filaments on said first and second sides of said gate electrode;

applying a third mask layer over said active portion to protect said first and second contact regions;

additionally doping said first and second regions of said active portion not protected by said first mask layer with dopant of a second conductivity type, said additionally doping step resulting in heavier doping concentration than said first doping step.

10. The method of claim 9, wherein said first and second contact regions are adjacent to said gate electrode.

11. The method of claim 9, wherein said first and second contact regions are not adjacent said gate electrode;

and wherein said third mask layer protects the doped region disposed between said first and second contact regions and said gate electrode.

12. The method of claim 6, wherein said first and second contact regions are adjacent to said gate electrode.