Vehicle multiplex system

• US 4,907,222 A
• Filed: 08/17/1988
• Issued: 03/06/1990
• Est. Priority Date: 08/17/1988
• Status: Expired due to Term

• Current Assignee: Intellitec Products, LLC
• Original Assignee: Nuvatec Incorporated
• Inventors: Slavik, William H.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US07/233,262
• Time in Patent Office: 566 Days
• Field of Search: 370/85, 370/95, 370/92, 370/77, 340/53, 340/52 R, 340/52 D, 340/22, 340/422.5, 307/10 R
• US Class Current: 370/443
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: B60R 2021/01075 between the airbag control unit and pyrotechnic fuses or equivalent actuators
• CPC Class Codes: B60R 2021/01115 specific data frames
• CPC Class Codes: H04J 3/06 Synchronising arrangements for television systems H04N5/04; bit-synchronisation H04L7/00
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 7/06 the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length

Abstract

A time division multiplex system for motor vehicles and other applications in which data signals are adapted to be sent through the system in cyclical fashion during each of a series of time periods. The system includes a communication line, a master unit connected to the communication line which includes a pulse-generating circuit for sending a plurality of timing signals out over the line for defining a plurality of time slots during each time period, and a plurality of transceiver units connected to the communication line. Each of the transceiver units is operable in either a transmit mode or a receive mode and includes an address-decoding circuit for identifying a selected one of the plurality of time slots on the line during each time period, a data-signal-transmitting circuit operable when the transceiver is in a transmit mode for sending the data signal out onto the line during the selected time slot, and a data-signal-receiving circuit operable when the transceiver is in a receive mode for receiving a data signal from the line during the selected time slot. With the system of the present invention, data can be transferred onto the line from any one transceiver and received from the line by any other transciever or transceivers to provide a system having a great deal of flexibility. The system also includes circuitry to permit power for the transceivers to be sent over the single communication line from the master unit.

Claims

1. A time division multiplex system in which data signals are adapted to be sent through the system in cyclical fashion during each of a series of time periods, comprising:

a communication line;

a master unit connected to said communication line, said master unit including a pulse-generating circuit for sending a plurality of timing signals out over said line for defining a plurality of time slots during each time period; and

a plurality of transceivers connected to said communication line, each of said transceivers being selectively operable in either a transmit mode to transmit data signals onto said line or in a receive mode to receive data signals from said line and including an address-decoding circuit for identifying a selected one of said plurality of time slots on said line during each time period, a data-signal-transmitting circuit operable when the transceiver is in a transmit mode for sending a data signal out onto said line during said selected time slot, and a data-signal-receiving circuit operable when the transceiver is in a receive mode for receiving a data signal from said line during said selected time slot, said data-signal-transmitting circuit and said data-signal-receiving-circuit including common circuit means for selectively connecting said address-decoding circuit to said data-signal transmitting circuit when said transceiver is operated in a transmit mode or to said data-signal-receiving circuit when said transceiver is operated in a receive mode.

2. The system of claim 1 wherein said address-decoding circuit includes a timing signal separator circuit for separating said timing signal from other signals on said line, and a counter coupled to said timing signal separator circuit for providing a counter output signal indicative of the presence of said selected time slot on said line during each time period.

3. The system of claim 2 wherein said common circuit means includes a gate having a first input connected to said counter, and wherein said data-signal-receiving circuit includes a data-signal separator circuit for separating data signals on said line from other signals on said line, said data-signal separator circuit being connected to a second input of said gate when said transceiver is in a receive mode for providing an output signal from said gate when a signal is received at both said first and second inputs to said gate indicative of the presence of a data signal on said line in said selected time slot, and wherein said data-signal-transmitting circuit includes a signal input means being connected to said second input of said gate when said transceiver is operated in a transmit mode for providing a gate output signal when a signal is received at both said first and second inputs to said gate, and means coupled to said gate output for sending a data signal onto said line during said selected time slot.

4. The system of claim 2 wherein said pulse-generating circuit includes a sync/clock pulse generator circuit for generating synchronizing timing signals having a first duration for identifying the first time slot of each time period and clock timing signals having a second duration for identifying the subsequent time slots of each time period, and wherein said address-decoding circuit further includes a comparator circuit for separating the synchronizing timing signals from said clock timing signals, said comparator circuit being connected to said counter for resetting said counter at the beginning of each time period.

5. The system of claim 3 wherein said counter includes a plurality of outputs each of which corresponds to a different one of said selected time slots and wherein said first input of said gate is connected to the output of said counter which corresponds to said selected time slot.

6. The system of claim 1 wherein said master unit includes means for normally maintaining the voltage on said line at a first elevated voltage level, wherein said pulse-generating circuit includes means for sending timing signals out over said line at a second elevated voltage level greater than said first voltage level, and wherein said data-transmitting circuit of each transceiver includes means for sending data signals over said line at a third voltage level which is less than said first voltage level.

7. The system of claim 6 wherein each of said transceivers further includes a power supply circuit for rectifying the timing signals on said line for providing power to said transceivers from said line.

8. The system of claim 6 wherein said first voltage is about nine volts, said second voltage is about twelve volts and said third voltage is about three volts.

9. The system of claim 1 wherein each of said time slots is about three milliseconds in length.

10. A time division multiples system in which data signals are adapted to be sent through the system in cyclical fashion during each of a series of time periods, comprising:

a communication line;

a master unit connected to said communication line and including timing signal-generating circuitry for sending a plurality of timing signals out over said line for defining a plurality of time slots during each time period;

a plurality of transceivers connected to said communication line, each of said transceivers being connected to a load and including;

an address-decoding circuit for separating said timing signals on said line from other signals on said line and for producing a first output signal indicative of the presence of a selected time slot on said line during each time period;

a data-signal-transmitting circuit for sending a data signal out onto said line during said selected time slot of each time period when said transceiver is operated in a transmit mode; and

a data-signal-receiving circuit for receiving a data signal from said line during said selected time slot of each time period when said transceiver is operated in a receive mode, said data-signal-receiving circuit including a data signal separator circuit for separating data signals from other signals on said line and for producing a second output signal indicative of the presence of data signals on said line,

said data-signal-transmitting circuit and said data-signal-receiving circuit including a common gate having a first gate input connected to the output of said address-decoding circuit and having a second gate input selectively connected to either said data separator circuit when said transceiver is being operated in a receive mode for providing a gate output signal when said first and second signals are received at said first and second gate inputs indicative of the presence of a data signal on said line in said selected time slot to permit control of said load, or to a signal input means when said transceiver is being operated in a transmit mode for providing a gate output signal when said first signal and said gate input signal are received at said first and second gate inputs to permit a data signal indicative of the condition of said load to be placed onto said line during said selected time slot.

11. The system of claim 10 wherein each of said transceivers further includes a power supply for rectifying said timing signal on said line for providing power to said transceivers.

12. The system of claim 10 wherein said address-decoding circuit includes a timing signal separator circuit for separating timing signals on said line from other signals on said line, and a counter connected to said timing signal separator circuit for counting said timing signals, said counter having a plurality of outputs which correspond to said plurality of time slots, and wherein a time slot is selected by coupling a selected one of said counter outputs to said first gate input.

13. A transceiver for a time division multiplex system which includes a communication line over which data signals are adapted to be sent through the system in cyclical fashion during each of a series of time periods, and timing means for sending a plurality of timing signals over said line for defining a plurality of time slots during each time period during which data signals can be sent over said line, said transceiver being adapted to be connected to said communication line and being selectively operable in either a transmit mode or in a receive mode and including:

an address-decoding circuit for identifying a selected one of said plurality of time slots on said line during each time period, said address-decoding circuit including means for providing an output signal indicative of said selected time slot;

a data-receiving circuit operable when said transceiver is in a receive mode for receiving a data signal from said line during said selected time slot, said data-receiving circuit including a data separator circuit for separating data signals on said line from others signals on said line, and a gate having a first input connected to said output signal providing means and a second input connected to the output of said data separator circuit when said transceiver is operated in a receive mode for providing a gate output signal when a signal is received at both said first and second gate inputs indicative of the presence of a data signal on said line in the selected time slot; and

a data-transmitting circuit operable when said transceiver is in a transmit mode for sending a data signal onto said line during said selected time slot, said data-transmitting circuit also including said gate, and wherein said second gate input is connected to a signal input means when said transceiver is operated in a transmit mode for providing a gate output signal when a signal is received at both said first and second gate inputs, and means coupled to said gate output for sending a data signal onto said line during said selected time slot.

14. The transceiver of claim 13 wherein said output signal providing means comprises a counter having a plurality of outputs each of which corresponds to a different one of said plurality of time slots, and wherein said first gate input is connected to the output of said counter which corresponds to said selected time slot.

15. The transceiver of claim 13 wherein said gate comprises a NAND gate.

16. The transceiver of claim 14 wherein said timing signals on said line include synchronizing signals for identifying the first time slot of each time period and clock signals for identifying each subsequent time slot of each time period, and wherein said output signal providing means further includes a clock/sync separator circuit for providing output sync signals indicative of said synchronizing signals, said counter being coupled to said clock/sync separator circuit for receiving said output sync signals for resetting said counter at the beginning of each time period.

17. The transceiver of claim 13 wherein said line is normally maintained at a first voltage level, said timing signals on said line are at a second voltage level greater than said first voltage level and said data signals on said line are at a third voltage level less than said first voltage level, and wherein said address-decoding circuit includes a first comparator circuit for comparing the signals on said line with a first reference voltage and for producing an output when said signals on said line are greater than said first reference voltage, and wherein said data separator circuit comprises a second comparator circuit for comparing the signals on said line with a second reference voltage and for producing an output when said signals on said line are less than said second reference voltage.

18. The transceiver of claim 13 wherein said transceiver further includes a power supply circuit for rectifying said timing signals on said communication line for providing power for said transceiver.