Analog memory for storing digital information

• US 4,910,706 A
• Filed: 08/04/1983
• Issued: 03/20/1990
• Est. Priority Date: 09/11/1972
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/520,277
• Time in Patent Office: 2,420 Days
• Field of Search: 365/45, 365/189, 365/230, 365/222, 365/189.01, 365/230.01
• US Class Current: 365/45
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/23094 Debounce key
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/35262 Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35381 : Convert in real time input peripheral data to processor data, ouput data format
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35588 : Pack, compress data efficiently in memory
• CPC Class Codes: G05B 2219/36227 : Assist operator to calculate unknown points, contours
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36395 : Load local computer program from host, data transfer ram to rom, BTR
• CPC Class Codes: G05B 2219/36502 : Ram for variable servo data, rom for fixed servo routine
• CPC Class Codes: G05B 2219/36506 : Store in Rom and Ram
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The present invention is directed to an analog memory for storing digital information in analog signal form. Typically, digital information is stored in digital signal form, where each digital bit is stored in a separate digital memory cell. In accordance with the present invention, an analog memory such as a charge transfer device (CTD), bubble memory, or magnetostrictive memory is used to store analog signals. Each analog signal is representative of a plurality of digital bits, thereby providing storage for a plurality of digital bits in each analog memory cell. Use of such an analog memory in combination with a digital system facilitates a hybrid memory, where digital information is stored in analog signal form. In one embodiment, a digital to analog converter is used to convert digital information from a digital processor to analog signal form for storage in an analog memory and an analog to digital converter is used to convert analog signals stored in an analog memory to digital signal form for processing with the digital processor. In another embodiment, an analog read only memory is used to store a program for a stored program digital computer in analog signal form. Storage of digital information in analog signal form increases the efficiency of storage because a plurality of digital bits can be stored in each memory cell. An embodiment having analog error compensation utilizes a reference signal for adaptive compensation of errors. Various systems using such memories are disclosed including signal processors, stored program computers, reverberation systems, and others.

Claims

1. A hybrid memory system for storing digital information in analog signal form, said system comprising:

shiftable memory means for storing a plurality of analog signals;

shifting means for shifting the stored analog signals; and

converter means for generating digital output signals in response to the stored analog signals.

2. The system as set forth in claim 1 above, wherein said memory means includes a charge transfer device for storing the plurality of analog signals.

4. The system as set forth in claim 1 above, wherein said memory means includes a magnetic bubble memory for storing the plurality of analog signals.

18. The system as set forth in claim 1 above, further comprising a digital processor for processing digital information in response to the digital output signals from said converter means and an analog input circuit for generating analog signals in response to the processed digital information from said digital processor means, wherein said memory means includes means for storing the plurality of analog signals in response to the analog signals from said analog input circuit.

19. The system as set forth in claim 1 above, further comprising digital data processor means for generating the digital information to be stored in said memory means in analog signal form in response to processing of the digital output signals.

3. The system as set forth in clain 1 above, wherein said memory means includes a magnetic disk memory for storing the plurality of analog signals.

5. A hybrid memory system for storing digital information in analog signal form, said system comprising:

memory means for storing a plurality of analog signals;

shifting means for shifting the stored analog signals;

a refresh circuit for refreshing the stored analog signals; and

converter means for generating digital output signals in response to the stored analog signals.

6. A hybrid memory system for storing digital information in analog signal form, said system comprising:

charge memory means for storing a plurality of multiple state charge signals having an information content related to the signal state;

means for refreshing the stored multiple state charge signals to reduce amplitude degradation;

shifting means for shifting the stored multiple state charge signals; and

converter means for generating digital output signals in response to the stored multiple state charge signals.

7. A memory system comprising:

input means for generating a digital input signal;

means for generating an analog signal in response to the digital input signal;

memory means for storing the analog signal generated with said generating means;

means for shifting the stored analog signal; and

converter means for generating a digital output signal in response to the stored analog signal.

9. The system as set forth in claim 7 above, wherein said memory means includes a read only memory for storing the analog signal.

10. The system as set forth in claim 7 above, wherein said stored analog signals are multiple state signals having an information content related to the signal state and wherein said memory means includes charge means for storing the multiple state signals as multiple state charge signals:

said system further comprising means for refreshing the stored multiple state signals to reduce charge leakage degradation.

20. The system as set forth in claim 7 above, wherein said analog signal generating means includes a digital to analog converter for generating analog signals to be stored in said analog memory in response to the digital input signal generated with said input means.

21. The system as set forth in claim 7 above, further comprising a stored program digital computer operating in response to a stored program, wherein the analog signal stored in said memory means includes a stored program for said operating of said digital computer.

22. The system as set forth in claim 7 above, wherein said memory means includes an analog read only memory for storing the analog signals.

23. The system as set forth in claim 7 above, wherein said memory means is a charge transfer device memory for storing the analog signal as a charge signal.

24. The system as set forth in claim 7 above, wherein said memory means is an analog magnetic bubble memory for storing the analog signal in magnetic bubble signal form.

25. The system as set forth in claim 7 above, wherein said memory means is a magnetostrictive delay line memory for storing the analog signal as a magnetostrictive signal.

8. A memory system comprising:

input means for generating a digital input signal;

means for generating an analog signal in response to the digital input signal;

memory means for storing the analog signal generated with said generating means;

means for shifting the stored analog signal;

converter means for generating a digital output signal in response to the stored analog signal;

refresh means for generating a reference signal in response to the analog signal stored in said memory means; and

means for reducing amplitude degradation of the analog signal stored in said memory means in response to the reference signal.

11. A memory system comprising:

digital means for generating at least one digital input signal;

means for generating analog signals in response to the digital input signal;

memory means for storing a plurality of the analog signals;

shifting means for shifting the stored analog signals; and

converter means for generating digital output signals in response to the stored analog signals.

30. The system as set forth in claim 11 above, further comprising a digital processor for processing digital signals in response to the digital output signals generated with said converter means and means for storing analog signals in said memory means in response to the processing of digital signals with said processor means.

32. The system as set forth in claim 11 above, wherein said memory means includes a read only memory for storing the analog signals.

33. The system as set forth in claim 11 above, further comprising a stored program digital computer for processing information under control of a stored program, wherein the analog signals stored in said memory means include analog stored program signals for control of said digital computer.

35. The system as set forth in claim 11 above, further comprising a digital processor for processing digital information and an analog memory input circuit for generating an analog input signal in response to the processed digital information from said digital processor;

wherein said memory means includes means for storing the plurality of analog signals in response to the analog input signal from said analog input circuit.

12. A memory system for storing analog information in response to digital input information, said system comprising:

memory means for storing information, said memory means including

(a) means for storing a plurality of analog signals and

(b) means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals; and

means for refreshing the degraded analog signals.

13. The memory system as set forth in claim 12 above, further comprising means for generating the analog signals stored in said memory means in response to a digital input signal and means for generating a digital output signal in response to refreshed analog signals.

14. A memory system for storing analog information in response to digital input information, said system comprising:

means for generating digital input information;

means for generating analog signals in response to the digital input information;

memory means for storing information, said memory means including

(a) means for storing the analog signals and

(b) means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals; and

means for refreshing the degraded analog signals.

15. A memory system for storing analog information, said system comprising:

memory means for storing information, said memory means including

(a) means for storing a plurality of analog signals and

(b) means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals;

means for refreshing the degraded analog signals; and

means for generating a digital output signal in response to the stored analog signals.

16. A memory system comprising:

memory means for storing a plurality of analog signals wherein the storing of the analog signals degrades the stored analog signals; and

means for refreshing the degraded analog signals.

17. A hybrid memory system for storing digital information in analog signal form, said system comprising:

shiftable memory means for storing a plurality of analog signals, wherein the plurality of analog signals stored in said memory means includes a stored program;

shifting means for shifting the stored analog signals;

converter means for generating digital output signals in response to the stored analog signals, wherein the digital output signals from said converter means include stored program digital output signals; and

a stored program digital computer for processing digital information under control of the stored program digital output signals.

26. A memory system comprising:

input means for generating a digital input signal;

means for generating an analog signal in response to the digital input signal;

memory means for storing the analog signal generated with said generating means, wherein said memory means includes means for shifting the stored analog signal and wherein the shifting of the stored analog signal degrades the stored analog signal;

means for refreshing the degraded analog signal degraded by the shifting, said refreshing means including

(a) means for generating an analog reference signal in response to the stored analog signal and

(b) means for performing the refreshing in response to the analog reference signal; and

converter means for generating a digital output signal in response to the stored analog signal.

27. A memory system comprising:

input means for generating a digital input signal;

means for generating an analog signal in response to the digital input signal;

memory means for storing the analog signal generated with said generating means;

means for shifting the stored analog signal;

converter means for generating a digital output signal in response to the stored analog signal; and

means for generating a reference signal in response to the stored analog signal from said memory means and means for reducing amplitude degradation of the stored analog signal in response to the reference signal.

28. A memory system comprising:

digital means for generating at least one digital input signal;

means for generating analog signals in response to the digital input signal;

memory means for storing a plurality of the analog signals;

shifting means for shifting the stored analog signals;

refresh means for reducing amplitude degradation of the stored analog signals; and

converter means for generating digital output signals in response to the stored analog signals.

29. A memory system comprising:

digital means for generating at least one digital input signal;

means for generating analog signals in response to the digital input signal;

memory means for storing a plurality of the analog signals;

shifting means for shifting the stored analog signals;

refresh means for reducing amplitude gradation of the stored analog signals, wherein said refresh means includes means for generating a digital number in response to at least one of the analog signals stored in said memory means, means for correcting the digital number to compensate for the signal degradation, and means for generating a corrected analog signal in response to the corrected digital number; and

converter means for generating digital output signals in response to the stored analog signals.

31. A memory system comprising:

digital means for generating at least one digital input signal;

means for generating analog signals in response to the digital input signal;

memory means for storing a plurality of the analog signals;

shifting means for shifting the stored analog signals;

refresh means for reducing amplitude degradation of the stored analog signals, wherein said refresh means includes

(a) means for generating a reference signal in response to at least one of the stored analog signals from said memory means and

(b) means for reducing amplitude degradation of the stored analog signals in response to the reference signal; and

converter means for generating digital output signals in response to the stored analog signals.

34. A memory system comprising:

digital means for generating at least one digital input signal;

means for generating analog signals in response to the digital input signal;

memory means for storing a plurality of the analog signals;

shifting means for shifting the stored analog signals;

converter means for generating digital output signals in response to the stored analog signals; and

a digital processor for processing digital information in response to the digital output signals from said converter means.