Architecture for an improved performance of a programmable logic device
First Claim
1. In a programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, an apparatus for operating on said inputs according to a stored program, comprising:
- a plurality of memory cells for storing said program;
a plurality of buffers, wherein each of said buffers is coupled to receive a selective one of said inputs and, if enabled, provides a corresponding output;
for each said buffer, a corresponding one of said memory cells is coupled to enable said buffer for passing said input signal as said corresponding output, wherein enablement of each said buffer is determined by a stored state of its corresponding memory cell and wherein said corresponding output from each said buffer provides for said plurality of outputs from said PLD.
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Accused Products
Abstract
A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and non-inverting buffer, wherein the memory cells are coupled to enable the buffers. The stored state of each of the memory cells determines if a corresponding buffer is to be activated. In one embodiment, a memory cell is provided for each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the outputs of each pair of complementary buffers are inputted to a multiplexer, wherein a corresponding memory cell coupled to its multiplexer controls the selection of the signal or its complement to be outputted.
67 Citations
18 Claims
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1. In a programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, an apparatus for operating on said inputs according to a stored program, comprising:
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a plurality of memory cells for storing said program; a plurality of buffers, wherein each of said buffers is coupled to receive a selective one of said inputs and, if enabled, provides a corresponding output; for each said buffer, a corresponding one of said memory cells is coupled to enable said buffer for passing said input signal as said corresponding output, wherein enablement of each said buffer is determined by a stored state of its corresponding memory cell and wherein said corresponding output from each said buffer provides for said plurality of outputs from said PLD. - View Dependent Claims (2, 3, 4, 5)
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6. A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, wherein said outputs are determined by a stored program operating on said inputs, comprising:
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a plurality of memory cells arranged in an array for storing said program; a plurality of buffers for buffering said inputs if enabled, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; for each said buffer, a corresponding one of said memory cells is coupled to enable its buffer for passing said input signal or its complement, wherein enablement of each said buffer is determined by a stored state of said corresponding memory cell. - View Dependent Claims (7, 8, 9, 10)
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11. A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising:
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a plurality of memory cells for storing said program; a plurality of buffers wherein each of said inputs is coupled to at least one of said buffers; a plurality of multiplexers (MUXs) each coupled to a corresponding buffer for receiving an output from its corresponding buffer as its input; for each said MUX, a corresponding one of said memory cells is coupled to enable said MUX for passing its input signal as an output from said MUX, wherein enablement of said MUX is determined by a stored state of said corresponding memory cell. - View Dependent Claims (12, 13, 14)
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15. A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising:
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a plurality of memory cells arranged in an array for storing said program; a plurality of buffers for buffering said inputs, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; a plurality of multiplexers (MUXs) each coupled to a corresponding pair of buffers to receive its input and its complement; for each said MUX, a corresponding one of said memory cells is coupled to select between its corresponding input or its complement, wherein selection of said MUX is determined by a stored state of said corresponding memory cell. - View Dependent Claims (16, 17, 18)
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Specification