Programmable sequencing device for controlling fast complex processes

• US 4,931,985 A
• Filed: 03/21/1988
• Issued: 06/05/1990
• Est. Priority Date: 04/22/1987
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Huon, Pierre, Glaise, Rene J.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/171,503
• Time in Patent Office: 806 Days
• Field of Search: 364/900 MS File, 364/140, 364/141
• US Class Current: 326/36
• CPC Class Codes: G05B 19/045 using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
• CPC Class Codes: G05B 19/07 where the programme is defined in the fixed connection of electrical elements, e.g. potentiometers, counters, transistors

Abstract

Described is a sequencing device comprising a plurality of shift register stages, a plurality of switches and an output bus which couples the outputs from the shift register stages to inputs of the switches. Each shift register stage includes a data input port coupled to a selected switch, a clock input port coupled to a clock control signal line and a clear input port coupled to a clear control signal line. The sequencing device may be set in at least one of a plurality of states by external events that are provided as input signals to the sequencing device through input bus (10).

Claims

1. A sequencing device which may be set into at least one selected state among a plurality of states, each state controlling the operation of a process in a machine, said selected state(s) depending upon external events which are provided as input signals to the sequencing device through an input bus (10), said device being characterized in that it comprises:

an output bus (12),

a number n of shift register stages (SR) equal to the number of states, each stage having a data input, a clock signal input, a clear input and an output which is coupled to the output bus,

means (16) for providing a clock signal on the clock signal input,

means (18) for providing a clear control signal on the clear input to reset the sequencing device,

switching means (SW-1 to Sw-n) coupled to the input bus and to the output bus and having n output lines (14-1 to 14-n), each one of said lines is coupled to a corresponding data input of one shift register stage, said switching means being conditionally responsive to input signals of the input bus and to signals on the output bus selected as a function of a desired sequence of states for generating an active signal on at least one of said n output lines, which is provided to the corresponding data input of the shift register stage which provides an active signal on its output under control of the clock signal, whereby the state of the sequencing device is set as a function of the states of the input signals and of its previous state.

2. Sequencing device according to claim 1, characterized in that the switching means comprise n logic arrangements, each one being conditioned by selected input signals of the input bus and by selected output signals of the output bus.

3. Sequencing device according to any one of claim 1 or 2, characterized in that one state of the sequencing device is an idle state indicated by a signal at the output of any stage dedicated to indicate this idle state, which becomes active in absence of external events or when none of the other stages is ON.