Time sliced vector processing

• US 4,939,638 A
• Filed: 02/23/1988
• Issued: 07/03/1990
• Est. Priority Date: 02/23/1988
• Status: Expired due to Fees

• Current Assignee: Stardent Computer, Inc.
• Original Assignee: Stellar Computer, Inc.
• Inventors: Normoyle, Kevin B., Stephenson, R. Ashley, Moriondo, Christopher
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US07/159,250
• Time in Patent Office: 861 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/244
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

Access by a plurality of instruction streams to a shared resource is managed by preassigning to each instruction stream, arbitration time slots in each of which only one instruction stream is eligible to request access to the resource.

Claims

1. A method for aiding management of access to a shared resource by a plurality of instruction streams executing in a pipelined manner in a synchronous-pipeline computer, comprising

preassigning arbitration time slots to each instruction stream,

allowing, in each one of said arbitration time slots, only the instruction stream to which said one arbitration time slot is preassigned to request access to said shared resource, and

determining whether an instruction stream that has requested access during its preassigned arbitration time slot will be granted access to said shared resources, said determining step including detecting whether said shared resource will be available, and denying access when said shared resource is not available.

2. The method of claim 1 further comprising

approving said one instruction stream for access to said resource only if said instruction stream is requesting access during one of said preassigned time slots and said resource will be available.

3. The method of claim 2 comprising

temporarily suspending execution of said one instruction stream, if said instruction stream is requesting access during one of said preassigned time slots and said resource will not be available, and thereafter, during a subsequent time slot preassigned to said stream, permitting said stream to again request access to said resource.

4. The method of claim 1 comprising

interleaving the preassigned time slots of different said instruction streams to assure that each said instruction stream regularly is eligible to request access.

5. The method of claim 1 wherein each stream includes instructions that have data associated with them for processing by said shared resource, and further comprising

providing to the resource during each preassigned slot the data for a present instruction in the stream associated with that preassigned slot so that if said stream is approved for access to said resource, said resource will be able to proceed to execute said present instruction without waiting for said data to become available.

6. The method of claim 1 wherein the execution of instructions in each said instruction stream proceeds in a sequence of a predetermined number of phases, and said preassigned time slots correspond to a prespecified one of said phases.

7. The method of claim 1 wherein said shared resource comprises a vector unit.

8. The method of claim 2 further comprising:

permitting said approved instruction stream to gain access to said resource and to use said resource for an arbitrary time duration that may exceed a duration of one of said arbitration time slots.