System and method for increasing memory performance

• US 4,954,951 A
• Filed: 12/13/1988
• Issued: 09/04/1990
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US07/283,661
• Time in Patent Office: 630 Days
• Field of Search: 364/200, 364/900
• US Class Current: 711/218
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The improved memory system can use various memories, such as CCDs and RAMs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.

Claims

1. A memory system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

2. A memory system comprising:

a memory having a plurality of memory chips and storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the memory in response to the more significant bits of the address; and

a scanout circuit coupled to the memory and to the address generator circuit and scanning out data stored by each of a plurality of memory chips in sequence in response to the less significant bits of the address.

3. A memory system comprises:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address;

an overflow circuit coupled to the address generator circuit and generating an overflow signal in response to an overflow to the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the overflow circuit and delaying generating of the address by the address generator circuit in response to the overflow signal.

4. A memory system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and

a comparitor circuit coupled to the address generator circuit and generating a comparitor signal in response to detection of a change in the more significant bits of the address.

5. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the more significant bits of the address; and

a chip select circuit coupled to the memory and to the address generator circuit and selecting one of the plurality of integrated circuit memory chips in response to the less significant bits of the address.

6. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the more significant bits of the address;

a chip select circuit coupled to the memory and to the address generator circuit and selecting one of the plurality of integrated circuit memory chips in response to the less significant bits of the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

7. A memory system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

a detector circuit coupled to the address generator circuit and generated a first detector signal condition in response to detection of a change in the more significant bits of the address generated by the address generator circuit and generating a second detector signal condition in response to detection of the absence of a change in the more significant bits of the address generated by the address generator circuit;

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the first detector signal condition; and

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address, said accessing circuit scanning out data stored by the memory at a higher data rate in response to the less significant bits of the address and re-addressing data stored by the memory at a lower rate in response to the more significant bits of the address.

8. A memory system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the memory in response to the more significant bits of the address; and

a scanout circuit coupled to the memory and to the address generator circuit and scanning out data stored by the memory in response to the less significant bits of the address.

9. A memory system comprising:

a memory storing data;

a clock generator circuit generating a clock signal;

an address generator circuit generating an address having less significant bits and more significant bits and operating in response to the clock signal;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and

a gated clock circuit coupled to the address generator circuit and gating the clock signal to delay generating of the address by the address generator in response to a change in the more significant bits of the address.

10. A Memory display system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address;

a display processor coupled to the accessing circuit and processing the data accessed by the accessing circuit to generate display data;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit;

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal; and

a display monitor coupled to the display processor and displaying an image in response to the display data generated by said display processor.

11. A memory artificial intelligence system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address;

an artificial intelligence processor coupled to the accessing circuit and processing the data accessed by the accessing circuit to generate artificial intelligence data;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

12. A memory television display system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address;

a television display processor for coupled to the accessing circuit and processing the data accessed by the accessing circuit to generate television display data;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit;

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal; and

a television monitor coupled to the television display processor and displaying a television image in response to the television display data generated by said television display processor.

13. A memory computer system comprising:

a first memory storing data;

a read only memory storing a computer program;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the first memory and to the address generator circuit and accessing data stored by the memory in response to the address;

a stored program computer coupled to the accessing circuit and to the read only memory processing the data accessed by the accessing circuit under control of the program stored by the read only memory;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

14. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips and storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the plurality of integrated circuit memory chips in response to the more significant bits of the address; and

a scanout circuit coupled to the memory and to the address generator circuit and scanning out data addressed in response to the more significant bits of the address that is stored by the plurality of integrated circuit memory chips by selecting each of a plurality of the integrated circuit memory chips in sequence in response to the less significant bits of the address.

15. A memory system comprising:

a plurality of RAMs storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the RAMs and to the address generator circuit and accessing data stored by the RAMs in response to the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address;

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generation of the address by the address generator in response to the detector signal;

a scanout address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal.

16. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an addressing circuit coupled to the integrated circuit memory and to the address generator circuit and addressing data stored by the integrated circuit memory in response to the more significant bits of the address;

a chip selection circuit coupled to the integrated circuit memory and to the address generator circuit and selecting an integrated circuit memory chip in response to the less significant bits of the address;

an accessing circuit coupled to the addressing circuit, to the chip selection circuit, and to the integrated circuit memory and outputting the data addressing in response to the more significant bits of the address from an integrated circuit memory chip selected by the less significant bits of the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit;

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal;

an external scanout address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by address generator circuit at a second address update rate that is lower than said first address update rate in response to a second state of the detector signal.

17. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

an accessing circuit coupled to the memory and to the address generator and reading data stored by the memory to generate memory output data in response to the address;

a processor coupled to the accessing circuit and processing the memory output data;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

18. A memory system as set forth in claim 17, further comprising:

a read-write controller generating a read-write signal to control reading and writing operations;

a first chip select controller coupled to the address generator circuit and generating a first chip select signal in response to the address;

a second chip select controller coupled to the address generator circuit and generating a second chip select signal in response to the address;

a clock pulse generator circuit generating a clock pulse signal;

wherein the memory includes a plurality of integrated circuit RAM chips;

wherein each of the RAM chips includes

(a) a plurality of memory locations storing data,

(b) an address circuit coupled to the plurality of memory locations and to the address generator circuit and addressing a memory location in response to the address,

(c) a read-write circuit coupled to the read-write controller and controlling reading and writing memory operations in response to the read-write signal,

(d) an access circuit coupled to the address circuit and to the read-write circuit and accessing the data stored by the memory location addressed by the address under control of the read-write signal,

(e) a data register coupled to the access circuit and storing the data accessed by the access circuit,

(f) a chip select circuit coupled to the first chip select controller and to the second chip select controller and selecting the related RAM chip in response to the first chip select signal and the second chip select signal, and

(g) a tri-state output circuit coupled to the access circuit and to the chip select circuit and outputting the data stored by the data register when the related RAM chip is select by the chip selected circuit;

wherein the address generator circuit includes a plurality of channels of address generator circuits each channel having an adder with a carry propagation circuit and coupled to the clock pulse generator circuit and generating a portion of the address by adding operands using carry propagation in response to the clock pulse signal and a concatenation circuit adapted to concatenate the portions of the address to generate the address,

wherein the processor includes a display processor coupled to the tri-state output circuit and processing the data output by the tri-state output circuit to generate a display signal;

wherein the detector circuit includes an overflow detector circuit coupled to the address generator circuit and generating the detector signal as an overflow detector signal in response to detection of an overflow in the carry propagation associated with the address generated by the address generator circuit; and

wherein the delaying circuit is further coupled to the clock pulse generator circuit and is adapted to delay generation of the address by the address generator circuit by gating of the clock pulse signal in response to the detector signal.

19. A memory system comprising:

a memory having a plurality of memory chips and storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the memory in response to the more significant bits of the address; and

a scanout circuit coupled to the memory and to the address generator circuit and scanning out data stored by each of a plurality of memory chips in sequence in response to the less significant bits of the address.

20. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

an overflow detector circuit coupled to the address generator circuit and generating an overflow detector signal in response to detection of an overflow in the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the overflow detector circuit and delaying generating of the address by the address generator circuit in response to the overflow detector signal.

21. A memory system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and

a comparitor circuit coupled to the address generator circuit and generating a comparitor signal in response to detection of a change in the address.

22. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips storing data;

an address generator circuit generating an address;

a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the address;

a chip select circuit coupled to the memory and to the address generator circuit and selecting one of the plurality of integrated circuit memory chips in response to the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

23. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the memory in response to the address; and

a scanout circuit coupled to the memory and to the address generator circuit and scanning out data stored by the memory in response to the address.

24. A memory system comprising:

a memory storing data;

a clock generator circuit generating a clock signal;

an address generator circuit generating an address in response to the clock signal;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and

a gated clock circuit coupled to the address generator circuit and gating the clock signal in response to the address.

25. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips and storing data;

an address generator circuit generating an address;

an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the plurality of integrated circuit memory chips in response to the address; and

a scanout circuit coupled to the memory and to the address generator circuit and scanning out data addressed in response to the address that is stored by the plurality of integrated circuit memory chips.

26. A memory system comprising:

a plurality of RAM chips storing data;

an address generator circuit generating an address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address generated by the address generator circuit;

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal;

a scanout address update circuit updating the address at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit updating the address at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal.

27. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips storing data;

an address generator circuit generating an address;

an addressing circuit coupled to the integrated circuit memory and to the address generator circuit and addressing data stored by the integrated circuit memory in response to the address;

a chip selection circuit coupled to the integrated circuit memory and to the address generator circuit and selecting an integrated circuit memory chip in response to the address;

an accessing circuit coupled to the addressing circuit, to the chip selection circuit, and to the integrated circuit memory and outputting the data addressed in response to the address from an integrated circuit memory chip selected by the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address generated by the address generator circuit;

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal;

an external scanout address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by address generator circuit at a second address update rate that is lower than said first address update rate in response to a second state of the detector signal.

28. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

a processor coupled to the memory and to the address generator circuit and processing data stored by the memory in response to the address generated by the address generator circuit; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to the address generated by the address generator.

29. A memory system comprising:

a memory having a plurality of memory chips and storing data;

an address generator circuit generating an address;

an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the memory in response to the address; and

a scanout circuit coupled to the memory and to the address generator circuit and scanning out data stored by each of a plurality of memory chips in sequence in response to the address.

30. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

an access circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and

an overflow circuit coupled to the address generator circuit and generating an overflow signal in response to detection of an overflow in the address generated by the address generator circuit.

31. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

an access circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address generated by the address generator circuit.

32. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips storing data;

an address generator circuit generating an address;

a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the address; and

a chip select circuit coupled to the integrated circuit memory and to the address generator circuit and selecting one of the plurality of integrated circuit memory chips in response to the address.

33. A memory system comprising:

an integrated circuit memory having a plurality of integrated circuit memory chips storing data;

an address generator circuit generating an address;

a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the address;

a chip select circuit coupled to the memory and to the address generator circuit and selecting one of the plurality of integrated circuit memory chips in response to the address; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address.

34. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

an accessing circuit coupled to the memory and to the address generator circuit and reading data stored by the memory in response to the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to the address generated by the address generator; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by said address generator circuit in response to the detector signal.

35. A memory system comprising:

a memory storing data;

a clock generator circuit generating a clock signal;

an address generator circuit generating an address in response to the clock signal; and

a gated clock circuit coupled to the clock generator circuit and to the address generator circuit and gating the clock signal in response to the address.

36. A memory system comprising:

a memory storing data;

an address generator circuit generating an address;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to the address generated by the address generator circuit;

a scanout address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by said address generator circuit at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit coupled to the address circuit and to the detector circuit and updating the address generated by said address generator at a second address update rate that is lower than said first address update rate in response to a second state of the detector signal.

37. A memory system comprising:

a plurality of RAM chips storing data;

an address generator circuit generating an address;

a processor coupled to the plurality of RAM chips and to the address generator circuit and processing data stored by the plurality of RAM chips in response to the address generated by the address generator circuit;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to the address generated by the address generator;

an external scanout address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal.

38. A memory system comprising:

a memory storing digital data;

an addressing circuit coupled to the memory and addressing the memory at a rate that is no greater than the addressing rate capability of the memory; and

an output circuit coupled to the memory and outputting digital data from said memory at a rate greater than the addressing rate capability of the memory.

39. A memory system as set forth in claim 38, wherein said memory includes a plurality of memory chips, wherein each of said plurality of memory chips includes a chip address circuit addressing a storage location in response to the address and a chip control circuit controlling the output of data stored in said storage location in response to a scanout signal;

wherein said addressing circuit includes a chip access circuit generating an address of data to be accessed from said memory;

wherein said addressing circuit includes a first address portion circuit generating a first portion of the address and a second address portion circuit generating a second portion of the address;

wherein the first portion of the address changes more rapidly than the second portion of the address;

wherein said addressing circuit further includes a memory access circuit controlling access of data from said memory, said memory access circuit including an input circuit applying the second portion of the address to said chip address circuit of each of said plurality of memory chips, a first scanout circuit generating a plurality of scanout signals in response to the first portion of the address, and a second scanout circuit applying the scanout signals to said chip control circuit of each of said plurality of memory chips.

40. A memory system as set forth in claim 38, wherein said memory includes a plurality of integrated circuit random access memory chips storing the digital data.

41. A memory system as set forth in claim 38, wherein said memory includes a plurality of integrated circuit random access memory chips storing the digital data, wherein said memory chips have an address input circuit coupled to the addressing circuit and operating in response to the address and a multiple dimensional control circuit outputting the digital data under control of the output circuit.

42. A memory system as set forth in claim 38, wherein said memory includes a plurality of integrated circuit random access memory chips storing the digital data, wherein said memory chips have an address input and a plurality of tristate output controls, wherein said addressing means includes means for addressing the address input, and wherein said outputting means includes multiple dimensional control means for controlling said plurality of tristate output controls with a plurality of dimensions of control signals.

43. A memory system comprising:

a plurality of memory chips storing digital data;

an addressing circuit coupled to the plurality of memory chips and addressing the plurality of memory chips at a rate that is no greater than the addressing rate capability of the plurality of memory chips; and

an output circuit coupled to each of the plurality of memory chips and outputting the digital data stored by the plurality of memory chips at a rate greater than the addressing rate capability of the memory by selecting one of the plurality of memory chips to output digital data and by selecting the other ones of the plurality of memory chips to not outputting digital data.

44. A memory system comprising:

a plurality of memory chips storing digital data;

an addressing circuit coupled to the plurality of memory chips and addressing the plurality of memory chips at a rate that is no greater than the addressing rate capability of the plurality of memory chips; and

an input circuit coupled to each of the plurality of memory chips and inputting the digital data stored by the plurality of memory chips at a rate greater than the addressing rate capability of the memory by selecting one of the plurality of memory chips to output digital data and by selecting the other ones of the plurality of memory chips to not store digital data.

45. A memory system comprising:

a memory storing digital data, wherein said memory includes a plurality of memory chips, wherein each of said plurality of memory chips has a tristate control circuit outputting the digital data to a data bus that is common to said plurality of memory chips in response to a tristate control signal;

an addressing circuit coupled to the memory and addressing the memory at a rate that is no greater than the addressing rate capability of the memory;

a data bus circuit coupled to the tristate control circuit of each of the memory chips and outputting digital data from the memory at a rate greater than the addressing rate capability of the memory; and

an output circuit coupled to the tristate control circuit of each of the plurality of memory chips and generating the tristate control signal to control the tristate control circuit of each of said plurality of memory chips for tristate selecting of one of said plurality of memory chips for outputting the digital data onto said data bus and for tristate selecting the others of said plurality of memory chips for not outputting digital data onto said data bus.

46. A memory system comprising:

a memory storing digital data, wherein said memory includes a plurality of integrated circuit random access memory chips storing the digital data, and wherein each of said memory chips has an address input circuit operating in response to an address and has a tristate output circuit operating under control of an output signal to output the digital data addressed by the address;

an addressing circuit coupled to the address input circuit of each of the memory chips and generating the address to address each of the memory chips at a rate that is no greater than the addressing rate capability of the memory; and

an output circuit coupled to the tristate output circuit of each of the memory chips and generating the output signal to output signal data from said memory at a rate greater than the addressing rate capability of the memory.

47. A memory system comprising:

a memory storing digital data, wherein said memory includes a plurality of memory chips, wherein each of said plurality of memory chips includes an address circuit addressing a storage location in response to an address and a control circuit controlling the output of data stored in said storage location in response to a scanout signal;

an address generator coupled to the memory and generating an address of data to be accessed from said memory, wherein said address generator includes a first address circuit generating a first portion of the address and a second address circuit generating a second portion of the address and wherein the first portion of the address changes more rapidly than the second portion of the address; and

a memory access circuit coupled to the memory and to the address generator and controlling access of data from said memory, said memory access circuit including an input circuit applying the second portion of the address to said address circuit of each of said plurality of memory chips, a scanout circuit coupled to the address generator and generating a plurality of scanout signals in response to the first portion of the address, and a memory input circuit applying the scanout signals to the control circuit of each of said plurality of memory chips.

48. A memory system as set forth in claim 47, wherein said address generator includes means for generating a plurality of address bits;

wherein said means for generating the first portion of the address includes the less significant bits of the plurality of address bits; and

wherein said means for generating the second portion of the address includes the more significant bits of the plurality of address bits.

49. A memory system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address;

a comparator circuit coupled to the address generator circuit and generating a comparator signal in response to detection of a change in the more significant bits of the address; and

a delaying circuit coupled to the address generator circuit and to the comparator circuit and delaying generation of the address by the address generator circuit in response to the comparitor signal.

50. A memory system comprising:

a memory storing data;

an address generator circuit generating an address having less significant bits and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and

a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the address.

51. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits and

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the less significant bits of the address and an address circuit addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address.

52. A memory system as set forth in claim 51, further comprising a memory output circuit outputting the data addressed by the address circuit from a selected integrated circuit memory chip.

53. A memory system comprising;

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the less significant bits of the address and an address circuit addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit.

54. A memory system comprising;

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the less significant bits of the address and an address circuit addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address; and

a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the more significant bits of the address generated by the address generator circuit.

55. A memory system comprising;

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the less significant bits of the address and an address circuit addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

56. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address; and

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the less significant bits of the address.

57. A memory system as set forth in claim 56, further comprising a memory output circuit outputting the data addressed by the chip addressing circuit from the selected integrated circuit memory chip.

58. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address;

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the less significant bits of the address; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit.

59. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address;

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the less significant bits of the address; and

a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the more significant bits of the address generated by the address generator circuit.

60. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the more significant bits of the address;

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the less significant bits of the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

61. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits and

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the more significant bits of the address and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the less significant bits of the address.

62. A memory system as set forth in claim 61, further comprising a memory output circuit outputting the data addressed by the chip address circuit from a selected integrated circuit memory chip.

63. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the more significant bits of the address and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the less significant bits of the address; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit.

64. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the more significant bits of the address and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the less significant bits of the address; and

a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the more significant bits of the address generated by the address generator circuit.

65. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the more significant bits of the address and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the less significant bits of the address;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

66. A memory system comprising:

an address generator circuit generating an address having less significant bits and more significant bits;

a first integrated circuit memory chip storing first data, said first integrated circuit memory chip including a first chip address circuit coupled to the address generator circuit and accessing data stored by the first integrated circuit memory chip in response to the more significant bits of the address and including a first chip selection circuit coupled to the address generator circuit and selecting the first integrated circuit memory chip in response to the less significant bits of the address;

a second integrated circuit memory chip storing second data, said second integrated circuit memory chip including a second chip address circuit coupled to the address generator circuit and accessing data stored by the second integrated circuit memory chip in response to the more significant bits of the address and including a second chip selection circuit coupled to the address generator circuit and selecting the second integrated circuit memory chip in response to the less significant bits of the address;

a third integrated circuit memory chip storing third data, said third integrated circuit memory chip including a third chip address circuit coupled to the address generator circuit and accessing data stored by the third integrated circuit memory chip in response to the more significant bits of the address and including a third chip selection circuit coupled to the address generator circuit and selecting the third integrated circuit memory chip in response to the less significant bits of the address; and

a forth integrated circuit memory chip storing forth data, said forth integrated circuit memory chip including a forth chip address circuit coupled to the address generator circuit and accessing data stored by the forth integrated circuit memory chip in response to the more significant bits of the address and including a forth chip selection circuit coupled to the address generator circuit and selecting the forth integrated circuit memory chip in response to the less significant bits of the address.

67. A memory system as set forth in claim 66, further comprising a memory output circuit outputting the data addressed by the chip address circuit from a selected integrated circuit memory chip.

68. A memory system as set forth in claim 66, further comprising a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit.

69. A memory system as set forth in claim 66, further comprising a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the more significant bits of the address generated by the address generator circuit.

70. A memory system as set forth in claim 66, further comprising:

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

71. A memory system comprising:

an address generator circuit generating a sequence of addresses;

a first integrated circuit memory chip coupled to the address generator and storing first data, said first integrated circuit memory chip generating first output data in response to a first address in the sequence of addresses;

a second integrated circuit memory chip coupled to the address generator and storing second data, said second integrated circuit memory chip generating second output data in response to a second address in the sequence of addresses;

a third integrated circuit memory chip coupled to the address generator and storing third data, said third integrated circuit memory chip generating third output data in response to a third address in the sequence of addresses; and

a forth integrated circuit memory chip coupled to the address generator and storing forth data, said forth integrated circuit memory chip generating forth output data in response to a forth address in the sequence of addresses.

72. A memory system comprising:

an address generator circuit generating a sequence of addresses, wherein each address in the sequence of addresses includes less significant bits and more significant bits and wherein the address generator circuit includes a sequential address generation circuit sequentially changing the less significant bits in the address;

a first integrated circuit memory chip coupled to the address generator and storing first data, said first integrated circuit memory chip generating first output data in response to a first address in the sequence of addresses;

a second integrated circuit memory chip coupled to the address generator and storing second data, said second integrated circuit memory chip generating second output data in response to a second address in the sequence of addresses;

a third integrated circuit memory chip coupled to the address generator and storing third data, said third integrated circuit memory chip generating third output data in response to a third address in the sequence of addresses;

a forth integrated circuit memory chip coupled to the address generator and storing forth data, said forth integrated circuit memory chip generating forth output data in response to a forth address in the sequence of addresses; and

a selection circuit coupled to the address generator circuit and to the integrated circuit memory chips and selecting each of the integrated circuit memory chips in sequence to generate the output data in response to the less significant bits of the address.

73. A memory system comprising:

an address generator circuit generating a sequence of addresses, wherein each address in the sequence of addresses includes less significant bits and more significant bits and wherein the address generator circuit includes a sequential address generation circuit sequentially changing the less significant bits in the address;

a first integrated circuit memory chip coupled to the address generator and storing first data, said first integrated circuit memory chip generating first output data in response to a first address in the sequence of addresses;

a second integrated circuit memory chip coupled to the address generator and storing second data, said second integrated circuit memory chip generating second output data in response to a second address in the sequence of addresses;

a third integrated circuit memory chip coupled to the address generator and storing third data, said third integrated circuit memory chip generating third output data in response to a third address in the sequence of addresses;

a forth integrated circuit memory chip coupled to the address generator and storing forth data, said forth integrated circuit memory chip generating forth output data in response to a forth address in the sequence of addresses;

an addressing circuit coupled to the address generator circuit and to the integrated circuit memory chips and addressing data stored in each of the integrated circuit memory chips; and

a selection circuit coupled to the address generator circuit and to the integrated circuit memory chips and selecting each of the integrated circuit memory chips in sequence to generate the addressed data as the output data in response to the less significant bits of the address.

74. A memory system comprising:

an address generator circuit generating a sequence of addresses;

a first integrated circuit memory chip coupled to the address generator and storing first data, said first integrated circuit memory chip generating first output data in response to a first address in the sequence of addresses;

a second integrated circuit memory chip coupled to the address generator and storing second data, said second integrated circuit memory chip generating second output data in response to a second address in the sequence of addresses;

a third integrated circuit memory chip coupled to the address generator and storing third data, said third integrated circuit memory chip generating third output data in response to a third address in the sequence of addresses;

a forth integrated circuit memory chip coupled to the address generator and storing forth data, said forth integrated circuit memory chip generating forth output data in response to a forth address in the sequence of addresses; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit.

75. A memory system comprising:

an address generator circuit generating a sequence of addresses;

a first integrated circuit memory chip coupled to the address generator and storing first data, said first integrated circuit memory chip generating first output data in response to a first address in the sequence of addresses;

a second integrated circuit memory chip coupled to the address generator and storing second data, said second integrated circuit memory chip generating second output data in response to a second address in the sequence of addresses;

a third integrated circuit memory chip coupled to the address generator and storing third data, said third integrated circuit memory chip generating third output data in response to a third address in the sequence of addresses;

a forth integrated circuit memory chip coupled to the address generator and storing forth data, said forth integrated circuit memory chip generating forth output data in response to a forth address in the sequence of addresses; and

a delaying circuit coupled to the addresses generator circuit and delaying generating of the address by the address generator circuit in response to the more significant bits of the address generated by the address generator circuit.

76. A memory system comprising:

an address generator circuit generating a sequence of addresses;

a first integrated circuit memory chip coupled to the address generator and storing first data, said first integrated circuit memory chip generating first output data in response to a first address in the sequence of addresses;

a second integrated circuit memory chip coupled to the address generator and storing second data, said second integrated circuit memory chip generating second output data in response to a second address in the sequence of addresses;

a third integrated circuit memory chip coupled to the address generator and storing third data, said third integrated circuit memory chip generating third output data in response to a third address in the sequence of addresses;

a forth integrated circuit memory chip coupled to the address generator and storing forth data, said forth integrated circuit memory chip generating forth output data in response to a forth address in the sequence of addresses;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

77. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently and

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the first address bits that change more frequently and an address circuit addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently.

78. A memory system as set forth in claim 77, further comprising a memory output circuit outputting the data addressed by the address circuit from a selected integrated circuit memory chip.

79. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the first address bits that change more frequently and an address circuit addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently.

80. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the first address bits that change more frequently and an address circuit addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently; and

a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the second address bits that change less frequently.

81. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips coupled to the address generator circuit and storing data, each integrated circuit memory chip having a select circuit selecting an integrated circuit memory chip in response to the first address bits that change more frequently and an address circuit addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

82. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently; and

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the first address bits that change more frequently.

83. A memory system as set forth in claim 82, further comprising a memory output circuit outputting the data addressed by the chip addressing circuit from the selected integrated circuit memory chip.

84. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently;

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the first address bits that change more frequently; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently.

85. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently;

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the first address bits that change more frequently; and

a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the second address bits that change less frequently.

86. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips storing data;

a chip addressing circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and addressing data stored by the integrated circuit memory chips in response to the second address bits that change less frequently;

a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the first address bits that change more frequently;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

87. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently and

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the second address bits that change less frequently and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the first address bits that change more frequently.

88. A memory system as set forth in claim 87, further comprising a memory output circuit outputting the data addressed by the chip address circuit from a selected integrated circuit memory chip.

89. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the second address bits that change less frequently and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the first address bits that change more frequently; and

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently.

90. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the second address bits that change less frequently and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the first address bits that change more frequently; and

a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the second address bits that change less frequently.

91. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a plurality of integrated circuit memory chips storing data, wherein each of the integrated circuit memory chips includes an address circuit coupled to the address generator circuit and accessing data stored by the integrated circuit memory chip in response to the second address bits that change less frequently and including a selection circuit coupled to the address generator circuit and selecting the integrated circuit memory chip in response to the first address bits that change more frequently;

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently; and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.

92. A memory system comprising:

an address generator circuit generating an address having first address bits that change more frequently and second address bits that change less frequently;

a first integrated circuit memory chip storing first data, said first integrated circuit memory chip including a first chip address circuit coupled to the address generator circuit and accessing data stored by the first integrated circuit memory chip in response to the second address bits that change less frequently and including a first chip selection circuit coupled to the address generator circuit and selecting the first integrated circuit memory chip in response to the first address bits that change more frequently;

a second integrated circuit memory chip storing second data, said second integrated circuit memory chip including a second chip address circuit coupled to the address generator circuit and accessing data stored by the second integrated circuit memory chip in response to the second address bits that change less frequently and including a second chip selection circuit coupled to the address generator circuit and selecting the second integrated circuit memory chip in response to the first address bits that change more frequently;

a third integrated circuit memory chip storing third data, said third integrated circuit memory chip including a third chip address circuit coupled to the address generator circuit and accessing data stored by the third integrated circuit memory chip in response to the second address bits that change less frequently and including a third chip selection circuit coupled to the address generator circuit and selecting the third integrated circuit memory chip in response to the first address bits that change more frequently; and

a forth integrated circuit memory chip storing forth data, said forth integrated circuit memory chip including a forth chip address circuit coupled to the address generator circuit and accessing data stored by the forth integrated circuit memory chip in response to the second address bits that change less frequently and including a forth chip selection circuit coupled to the address generator circuit and selecting the forth integrated circuit memory chip in response to the first address bits that change more frequently.

93. A memory system as set forth in claim 92, further comprising a memory output circuit outputting the data addressed by the chip address circuit from a selected integrated circuit memory chip.

94. A memory system as set forth in claim 92, further comprising a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently.

95. A memory system as set forth in claim 92, further comprising a delaying circuit coupled to the address generator circuit and delaying generating of the address by the address generator circuit in response to the second address bits that change less frequently.

96. A memory system as set forth in claim 92, further comprising:

a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the second address bits that change less frequently and

a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal.