Conditional motion compensated interpolation of digital motion video

• US 4,958,226 A
• Filed: 09/27/1989
• Issued: 09/18/1990
• Est. Priority Date: 09/27/1989
• Status: Expired due to Term

• Current Assignee: Multimedia Patent Trust
• Original Assignee: AT&T, Inc.
• Inventors: Puri, Atul, Haskell, Barin G.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Kostak, Victor R.
• Application Number:
  US07/413,520
• Time in Patent Office: 356 Days
• Field of Search: 358/135, 358/136, 358/133
• US Class Current: 375/240.12
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/51 Motion estimation or motion compensation
• CPC Class Codes: H04N 19/577 Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

Motion digital video is encoded and decoded by a motion compensated interpolation method and apparatus. In accordance with the method, selected frames of the video are interpolated in the decoder with the aid of interpolation correction codes that are generated in the encoder and sent to the decoder. In an encoder embodiment that interpolates half of the frames, every other frame is encoded and decoded within the encoder. The decoded versions of adjacent frames are appropriately combined and compared to the interleaved camera frame that is to be interpolated in the decoder. The differences, which correspond to "pels correction" information, are encoded and quantized. Those that exceed a predetermined threshold value are added to the encoder'"'"'s output buffer. The inverse operation is carried out in the decoder. That is every pair of decoded frames is averaged and combined with the decoded "pels correction" information to form the interpolated frames.

Claims

1. A circuit for encoding applied video signals that comprise successive frames, where each frame is divided into blocks, comprising:

first means for encoding the blocks of some of said frames by developing for each block of such frames (a) and approximated version of said block derived from an approximated version of said block developed for a previous frame, and (b) a code which represents the deviation of said block from said approximated version of said block;

second means for approximating the blocks of those of said frames that are to be interpolated by combining approximated versions of said blocks in selected ones of the frames that are encoded in said first means; and

third means responsive to said second means and to said frames to be interpolated for developing a code that corresponds to those pels in blocks approximated by said second means that differ from corresponding pels in said frames to be interpolated by greater than a preselected threshold.

2. A circuit for encoding applied video signals that comprise successive frames, where each frame is divided into blocks, including means for encoding the blocks of some of said frames by developing for each block of such frames (a) an approximated version of said block derived from an approximated version of said block developed for a previous frame, and (b) a code which represents the deviation of said block from said approximated version of said block, the improvement comprising:

second means for approximating the blocks of those of said frames that are to be interpolated by combining approximated versions of said blocks in selected ones of the frames that are encoded in said means for encoding; and

third means responsive to said second means and to said frames to be interpolated for developing code that corresponds to those pels in blocks approximated by said second means that differ from corresponding pels in said frames to be interpolated by greater than a preselected threshold.

3. The circuit of claim 2 wherein said code developed for a pel by said third means represents the difference between the value of said pel and the value of said pel approximated by said second means.

4. The circuit of claim 2 wherein the frames selected for combining in said second means include a frame encoded in said first means that precedes the frame approximated in said second means and a frame encoded in said first means that succeeds the frame approximated in said means.

5. The circuit of claim 4 wherein said combining includes developing anticipated versions of said blocks.

6. The circuit of claim 2 wherein a set proportion of frames of said applied video signals are interpolated.

7. The circuit of claim 6 wherein said proportion is approximately one half.

8. The circuit of claim 2 fruther comprising buffer means for interposed between the codes developed by said means for encoding and said third means and an output port of said circuit.

9. The circuit of claim 8 for controlling the proportion of frames selected for interpolation by said second means and code generation by said third means based on the occupancy level of said buffer.

10. The circuit of claim 8 for selecting frames for interpolation by said second means and code generation by said third means when said buffer is occupied beyond a chosen proportion of its capacity.

11. The circuit of claim 7 wherein granularity of the codes generated by said first means and said third means is controlled by the occupancy level of said buffer.

12. A circuit responsive to coded video signals where the video signals comprise successive frames and each frame includes a plurality of blocks and where the coded video signals comprise codes that describe deviations from approximated blocks and codes that describe deviations from interpolated blocks, comprising:

means for developing block approximations from said codes that describe deviations from approximated blocks; and

means responsive to said block approximations and to said codes that describe deviations from interpolated blocks to develop said interpolated blocks.