Method of and system for power line carrier communications

• US 4,968,970 A
• Filed: 04/26/1989
• Issued: 11/06/1990
• Est. Priority Date: 04/26/1989
• Status: Expired due to Term

• Current Assignee: Itron, Inc.
• Original Assignee: Schlumberger Industries Incorporated (Schlumberger NV)
• Inventors: LaPorte, Eric
• Primary Examiner(s): Crosland, Donnie L.
• Application Number:
  US07/343,202
• Time in Patent Office: 559 Days
• Field of Search: 340/310 A, 340/310 R, 340/310 CP, 340/538, 340/825.06, 340/825.07, 340/825.08, 340/825.2, 375/1, 375/36, 375/37, 371/2, 371/5, 371/47, 371/48, 371/2.1, 371/2.2, 371/5.1, 371/6, 371/47.1, 371/48
• US Class Current: 375/133
• CPC Class Codes: H02J 13/00009 using pulsed signals
• CPC Class Codes: H04B 1/713 using frequency hopping
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/5433 Remote metering
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 2203/5491 using filtering and bypassing
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: Y02E 60/00 Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
• CPC Class Codes: Y04S 40/121 using the power network as support for the transmission

Abstract

The transmitter in a power line communications system applies to the power line encoded logical-one and logical-zero bit signals consisting of signals formed respectively of predetermined different sequences of frequencies. The receiver, coupled to the power line, includes a first homodyne, non-coherent, quadratic demodulator for demodulating the logical-one bits and a second for demodulating the logical-zero bits. The first demodulator produces, locally, and in first and second channels, respectively, a first reference signal that is a replica of the logical-one bit sequence of frequencies and a second reference signal that is the replica in quadrature. The second demodulator produces, locally, and in third and fourth channels, respectively, cooresponding third and fourth reference signals for the logical-zero bit sequence. Each of the four reference signals is applied to a corresponding analog multiplier for multiplication by the input signal in each channel. The output of each multiplier is applied to a low pass filter that passes only the dc component of the product signal which in turn is squared. The resultant signals in the first and second channels are summed to provide a first output signal, and the resultant signals in the third and fourth channels are summed to provide a second output signal. Compensation circuitry cancels error voltages developed in the demodulatin channels as a result of component offset, and the two output signals are integrated over a bit period and then compared to each other to detect a logical-one or logical-zero bit.

Claims

1. A system for wideband transmission of data on an electricity distribution network, comprising:

at least one transmitter including means for generating encoded signals corresponding respectively to logical-one bits and logical-zero bits, each encoded signal corresponding to a logical-one bit consisting of a first predetermined, unrelated sequence of frequencies and each encoded signal corresponding to a logical-zero bit consisting of a second, different predetermined and unrelated sequence of frequencies;

means for coupling said encoded signals on said electricity distribution network; and

at least one receiver having means for receiving from said at least one transmitter, input encoded signals on said electricity distribution network, and a homodyne, non-coherent demodulator including

(a) first demodulator means having first and second channels for demodulating said logical-one bit signals, said first demodulator means comprising, (i) in said first channel, a first local signal generator means for providing a first reference signal that is a replica of said encoded logical-one bit signal, first multiplier means for forming a product of said input encoded signal and said first reference signal, first filter means coupled to an output of said first multiplier means for passing substantially only a first dc component therefrom, and first squaring means for squaring said first dc component, and (ii) in said second channel, a second local signal generator means for providing a second reference signal that is, in quadrature, a replica of said encoded logical-one bit signal, second multiplier means for forming a product of said input encoded signal and said second reference signal, second filter means coupled to an output of said second multiplier means for passing substantially only a second dc component therefrom, second squaring means for squaring said second dc component;

first summer means for summing outputs of said first and second squaring means and first integrator means for accumulating from said first summer means first output signals corresponding to said first sequence of frequencies,

(b) second demodulator means having third and fourth channels for demodulating said logical-zero bit signals, said third demodulator means comprising, (i) in said third channel, a third local signal generator means for providing a third reference signal that is a replica of said encoded logical-zero bit signal, third multiplier means for forming a product of said input encoded signal and said third reference signal, third filter means coupled to an output of said third multiplier means for passing substantially only a third dc component therefrom, and third squaring means for squaring said third dc component, and (ii) in said fourth channel, a fourth local signal generator means for providing a fourth reference signal that is, in quadrature, a replica of said encoded logical-zero bit signal, fourth multiplier means for forming a product of said input encoded signal and said fourth reference signal, fourth filter means coupled to an output of said fourth multiplier means for passing substantially only a fourth dc component therefrom;

fourth squaring means for squaring said fourth dc component;

second summer means for summing outputs of said third and fourth squaring means and second integrator means for accumulating from said second summer means second output signals corresponding to said second sequence of frequencies, and

(c) comparator means for comparing output signals from said first and second integrator means for indicating a logical-one or logical-zero bit.

2. The system of claim 1, including synchronization means for synchronizing said at least one receiver with said at least one transmitter.

3. The system of claim 1, wherein said at least one receiver and said at least one transmitter are synchronized to electricity on said electricity distribution network.

4. The system of claim 3, wherein said synchronization means includes zero crossing detector means synchronized to zero crossings of electricity on said electricity distribution network for generating line synchronization pulses.

5. The system of claim 4, including a phase locked loop responsive to said line synchronization pulses for controlling said encoded signals generating means.

6. The system of claim 1, including limiter means for limiting said input signal applied to said receiver.

7. The system of claim 1, including transformer means for coupling said encoded signals from said electricity distribution network to said receiver, and further including a band pass filter between said transformer and said receiver.

8. The system of claim 1, wherein said encoded signals generating means includes first and second frequency synthesizers for generating respectively said logical-one and logical-zero encoded signals.

9. The system of claim 1, wherein each of said sequences consists of four frequency "hops".

10. The system of claim 9, wherein the integration period of each of said first and second integrator means is four said "hops".

11. The system of claim 1, including offset compensation means for compensating said receiver for an error voltage developed as a result of receiver component offsets.

12. The system of claim 11, wherein said offset compensation means includes means for shunting an input of said receiver to provide a "zero input" thereto whereby the output voltage developed by said receiver is attributed only to offset voltage produced therein, means for latching said output offset voltage and means responsive to said latching means for compensating the output of said receiver.

13. A method of wideband transmission of data on an electricity distribution network, comprising the steps of:

generating encoded signals corresponding respectively to logical-one bits and logical-zero bits, each encoded signal corresponding to a logical-one bit consisting of a first predetermined, unrelated sequence of frequencies and each encoded signal corresponding to a logical-zero bit consisting of a second, different predetermined, unrelated sequence of frequencies;

coupling said encoded signals on said electricity distribution network; and

receiving input encoded signals on said electricity distribution network, said step of receiving including the steps of

(a) establishing first and second frequency channels for demodulating said logical-one bit signals and third and fourth channels for demodulating said logical-zero bit signals;

(b) in said first channel, providing a first reference signal that is a replica of said encoded logical-one bit signal, forming a first product signal that is a product of said input encoded signal and said first reference signal, filtering said first product signal for passing substantially only a first dc component thereof and squaring said first dc component to obtain a first output signal;

(c) in said second channel, providing a second local signal that is, in quadrature, a replica of said encoded logical-one bit signal, forming a second product signal that is a product of said input encoded signal and said second reference signal, filtering said second product signal for passing substantially only a second dc component thereof and squaring said second dc component to obtain a second output signal;

(d) in said third channel, providing a third reference signal that is a replica of said encoded logical-zero bit signal, forming a third product of said input encoded signal and said third reference signal, filtering said third product signal for passing substantially only a third dc component thereof and squaring said third dc component to obtain a third output signal; and

(e) in said fourth channel, providing a fourth reference signal that is, in quadrature, a replica of said encoded logical-zero bit signal, forming a fourth product of said input encoded signal and said fourth reference signal, filtering said fourth product signal for passing substantially only a fourth dc component thereof and squaring said fourth dc component to obtain a fourth output signal;

(f) summing said first and second output signals to obtain a first summed output signal corresponding to said first sequence of frequencies;

(g) summing said third and fourth output signals to obtain a second summed output signal corresponding to said second sequence of frequencies;

(h) integrating said first summed signal to obtain a first integrated output signal;

(i) integrating said second summed signal to obtain a second integrated output signal; and

(j) comparing said first and second integrated output signals for indicating a logical-one or logical-zero bit.

20. The method of claim 13, wherein said step of generating encoded signals includes generating first and second frequency synthesized signals corresponding respectively to said logical-one and logical-zero encoded signals.

21. The method of claim 13, wherein each of said sequences consists of four frequency "hops".

22. The system of claim 21, wherein the integration period of each of said first and second integration steps is four said "hops".

14. The method of claim 14, including the steps of synchronizing the transmitting and receiving steps.

15. The method of claim 14, wherein said synchronizing step comprises synchronizing the transmitting and receiving steps to electricity on said electricity distribution network.

19. The method of claim 14, including the step of coupling said encoded signals from said electricity distribution network and further including band pass filtering encoded signals coupled from said network.

16. The method of claim 16, wherein said synchronization step includes the step of zero crossing detection synchronized to zero crossings of electricity on said electricity distribution network for generating line synchronization pulses.

17. The method of claim 16, including the step of using said line synchronization pulses for controlling said step of generating said encoded signals.

18. The method of claim 17, including the step of limiting the magnitude of said input encoded signals.

23. A system for wideband transmission of data on an electricity distribution network, comprising:

at least one transmitter including means for generating encoded signals corresponding respectively to logical-one bits and logical-zero bits, each encoded signal corresponding to a logical-one bit consisting of a first predetermined, unrelated sequence of frequencies and each encoded signal corresponding to a logical-zero bit consisting of a second, different predetermined, unrelated sequence of frequencies;

means for coupling said encoded signals on said electricity distribution network;

at least one receiver having means for receiving from said at least one transmitter, input encoded signals on said electricity distribution network, and a homodyne demodulator including first demodulator means in a first frequency channel means for converting said logical-one bit signals into corresponding first dc signals, second demodulator means in a second frequency channel means for converting said logical-zero signals into corresponding second dc signals;

offset compensation means coupled to said receiver for compensating any error voltage developed by said receiver as a result of offset voltage produced by components of said receiver; and

comparator means for comparing output signals from said first and second channel means for indicating a logical-one or logical-zero bit.

24. The system of claim 23, wherein said offset compensation means includes means for shunting an input of said receiver to provide a "zero input") thereto whereby an output voltage developed by said receiver is attributed only to offset voltage produced therein, means for latching said output offset voltage and means responsive to said latching means for compensating an output of said receiver.

25. The system of claim 24, wherein said input shunting means comprises a first switch, and wherein said offset compensation means further includes a differential amplifier means, second switch means for supplying an uncompensated output voltage from said receiver to one input of said differential amplifier means and third switch means for supplying an output of said latch means to another input of said differential amplifier means.

26. The system of claim 24, wherein said first demodulator means has first and second channels for demodulating said logical-one bit signals, said first demodulator means comprising, (i) in said first channel, a first local signal generator means for providing a first reference signal that is a replica of said encoded logical-one bit signal, first multiplier means for forming a product of said input encoded signal and said first reference signal, first filter means coupled to an output of said first multiplier means for passing substantially only a first dc component therefrom, and first squaring means for squaring said first dc component, and (ii) in said second channel, a second local signal generator means for providing a second reference signal that is, in quadrature, a replica of said encoded logical-one bit signal, second multiplier means for forming a product of said input encoded signal and said second reference signal, second filter means coupled to an output of said second multiplier means for passing substantially only a second dc component therefrom, second squaring means for squaring said second dc component;

first summer means for summing outputs of said first and second squaring means and first integrator means for accumulating from said first summer means first output signals corresponding to said first sequence of frequencies,

and wherein said second demodulator means has third and fourth channels for demodulating said logical-zero bit signals, said third demodulator means comprising, (i) in said third channel, a third local signal generator means for providing a third reference signal that is a replica of said encoded logical-zero bit signal, third multiplier means for forming a product of said input encoded signal and said third reference signal, third filter means coupled to an output of said third multiplier means for passing substantially only a third dc component therefrom, and third squaring means for squaring said third dc component, and (ii) in said fourth channel, a fourth local signal generator means for providing a fourth reference signal that is, in quadrature, a replica of said encoded logical-zero bit signal, fourth multiplier means for forming a product of said input encoded signal and said fourth reference signal, fourth filter means coupled to an output of said fourth multiplier means for passing substantially only a fourth dc component therefrom;

fourth squaring means for squaring said fourth dc component;

second summer means for summing outputs of said third and fourth squaring means and second integrator means for accumulating from said second summer means second output signals corresponding to said second sequence of frequencies.

27. The system of claim 26 wherein at least said first through fourth squaring means, said first and second summing means, said first and second integrator means and said comparator means are software implemented.