Memory interface controller

• US 4,970,636 A
• Filed: 01/23/1989
• Issued: 11/13/1990
• Est. Priority Date: 01/23/1989
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Fischer, Douglas A., Woods, Jordon W., Snodgrass, Thomas D., Graves, Jennifer A.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Nguyen, Phu K.
• Application Number:
  US07/299,794
• Time in Patent Office: 659 Days
• Field of Search: 364/518, 364/521, 364/200 MS File, 364/900 MS File, 340/747, 340/750, 340/798, 340/799, 340/723, 340/727, 382/46
• US Class Current: 345/623
• CPC Class Codes: G06T 15/30 Clipping
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A memory interface controller apparatus for use in a digital system, such as a graphics display system. The apparatus comprises apparatus for receiving incoming pixel data and apparatus for detecting pixel address collision. In an alternate embodiment, apparatus for performing hidden surface removal on the incoming pixel data is included. The memory interface controller apparatus further may include apparatus for construction of images with transparent objects.

Claims

1. A memory interface controller apparatus for use in a graphics display system which includes a digital memory and a display screen having a viewable screen area and which receives serial input data representing a plurality of pixels and pixel addresses comprising:

(a) first register means for receiving and latching the input data and presenting the input data at an output;

(b) means for clipping connected to the output of the first register means wherein the clipping means clips the input data to retain clipped data having clipped data addresses only within the viewable screen area, wherein the clipping means has an output for passing the clipped data and clipped data addresses;

(c) second register means for receiving clipped data from the clipping means output wherein the second register means includes an output for passing the clipped data;

(d) third, fourth, fifth and sixth register means, each including an output, wherein the third register means has a first input connected to the output of the second register means, the fourth register means has an input connected to the output of the third register means, the fifth register means has an input connected to the output of the fourth register means, and the sixth register has an input connected to the output of the first register means wherein the third through sixth register means cooperates so as to serially pass the clipped data and the clipped data addresses;

(e) seventh register means for passing clipped data having an input and an output;

(f) means for calculating a K factor for the clipped data wherein the calculating means has a first stage and a second stage wherein the first stage is connected between the output of the sixth register means, and the input of the seventh register means, and wherein the second stage is connected to the output of the seventh register means; and

(g) means for preventing address collisions arranged to receive data from the third through seventh registers and further including means for comparing the clipped data address in the third register to the clipped data addresses in the fourth through seventh registers, means for identifying identical clipped data addresses, means for clearing the contents of the fourth through seventh register means if an identical address is identified, and means for halting data flow at the third register until the fourth through seventh register means are cleared.

2. The apparatus of claim 1 further including means for operating the memory interface controller apparatus in an asynchronous mode.

3. The apparatus of claim 1 further including means for buffering pixel Z-depth data and comparing the Z-depth of one pixel against another.

4. The apparatus of claim 3 further including a means for storing a look-up table having internal values of K and 1-K in 1/16 increments ranging from 0 to 1, wherein the look-up table is arranged to transmit K factors to the 5th and 6th register means.