Semiconductor high-power mosfet device

• US 4,974,059 A
• Filed: 08/28/1989
• Issued: 11/27/1990
• Est. Priority Date: 12/21/1982
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): Loke, Steven
• Application Number:
  US07/399,345
• Time in Patent Office: 456 Days
• Field of Search: 357/23.4, 357/23.8, 357/38, 357/52, 357/55
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A high power MOSFET is disclosed in which a plurality of hexagonal base regions formed in the surface of a chip receive respective hexagonal annular source regions. The base regions are relatively shallow and of relatively low conductivity material. A central portion of each of the base regions reaches the upper surface of the wafer and contacts a sheet source electrode which also contacts the source regions. The central regions of the base elements which contact the source electrode are of higher conductivity than the main base portion for a distance extending just below the depth of the source regions. The base regions are formed by ion implantation through a gate oxide which is exposed by a window in an overlying polysilicon layer. After ion implantation and driving of the base regions, an annular source region is diffused into each base, employing the same polysilicon window as an outer mask. A central oxide dot may be left in the center of each of the open windows so that the oxide is thicker at the central regions and remains in place during the diffusion of the source regions.

Claims

1. In a high power metal oxide semiconductor field effect transistor device comprising:

a semiconductor chip having first and second parallel opposite surfaces;

an upper layer on said chip of a relatively low conductivity region of one of the conductivity types extending to said first surface;

a plurality of substantially identical polygonal base regions of the other of said conductivity types extending from said first surface into said upper layer, said plurality of base regions being symmetrically laterally disposed over said first surface and having peripheries which are spaced from peripheries of adjacent base regions by a given distance;

a respective generally annular source region extending from said first surface into each of said base regions;

the lateral outer periphery of each of said source regions being laterally spaced along said first semiconductor surface from the lateral outer periphery of its said respective base region, thereby to define respective channels of the opposite conductivity type which can be inverted;

a gate oxide extending over each of said channels and a gate electrode atop said gate oxide; and

source electrode means connected to each of said source regions and to respective adjoining portions of their associated base regions at respective contact areas;

the improvement comprising, in combination with the foregoing;

said polygonal base regions each having a depth of less than about 0.25 mil, having a flat bottom portion substantially coextensive with the area of said base region at said first surface, and being free of any further portion extending deeper than said flat bottom portion;

a central region of each of said base regions having a lower extent situated above its associated flat bottom portion and an upper extent coextensive with said first surface and being in contact with said source electrode means, said central region having an increased conductivity compared to that of the remainder of said base region, said central region being deeper than its associated source region and extending laterally at least coextensively with the associated source electrode contact area;

said central region extending laterally beneath at least a portion of its said source region, thereby to reduce the lateral electrical resistance of the source region beneath at least a portion of the lateral extent of said source.

2. The device of claim 1, wherein said base regions have a hexagonal periphery.

3. The device of claim 1, wherein the space between the outer peripheries of said base regions and for a given depth below said first surface has a conductivity substantially greater than that of said upper layer of relatively low conductivity region.

4. The device of claim 3, wherein said base regions have a hexagonal periphery.

5. The device of claim 3 which further includes a drain electrode connected to said second surface.

6. The device of claim 1 which further includes a drain electrode connected to said second surface.

7. The device of claim 1, wherein the spacing between the lateral centers of adjacent ones of said base regions define a cell repeat distance, said cell repeat distance being less than about 26 microns.

8. The device of claim 1, wherein said base region extends into said semiconductor chip for a depth substantially less than 5 microns.

9. The device of claim 1, wherein said base region extends into said semiconductor chip for a depth of about 3 microns.