Programmable memory data protection scheme

• US 4,975,878 A
• Filed: 09/18/1989
• Issued: 12/04/1990
• Est. Priority Date: 01/28/1988
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Boddu, Sudhakar, Lucero, Elroy M., Kowshik, Vikram
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/409,958
• Time in Patent Office: 442 Days
• Field of Search: 365/195, 365/228, 365/185, 365/189.07, 365/230.08, 364/200 MS File, 364/900 MS File
• US Class Current: 365/189.07
• CPC Class Codes: G06F 12/1441 for a range

Abstract

An integrated, non-volatile memory protect register is provided for the memory array of a monolithic integrated circuit device. The memory array includes a plurality of programmable data storage registers, each having an associated address. The storage register addresses define the storage registers sequentially from an initial register in the array to a final register in the array. The memory protect register stores the address of a preselected storage register in the array. All registers in the array having addresses equal to or greater than the address of the preselected register are protected from any write operation. This address can be "locked" into the memory protect register to provide permanent data security to all protected registers.

Claims

1. An electrically erasable programmable read only memory (EEPROM) device that includes a memory array comprising a plurality of electrically erasable programmable read only memory data storage registers for storing data, each data storage register having a corresponding access address associated therewith, the access addresses defining the data storage registers sequentially from an initial data storage register to a final data storage, the EEPROM device further including means responsive to a read access address for reading data stored in a data storage register corresponding to the read access address, means responsive to an erase access address for electrically erasing data stored in a data storage registers corresponding to the erase access address, and means responsive to a write access address for altering data stored in a data storage register corresponding to the write access address, the EEPROM device further comprising:

(a) a programmable memory protect register that stores the access address of a selected data storage register as a protect address, the protect address defining a sequence of data storage registers having addresses equal to or greater than the address of the selected data storage resister;

(b) means responsive to the protect address for prohibiting alteration of data stored in the sequence of data storage registers defined by the protect address; and

(c) means for permanently locking the protect address into the memory protect register thereby permanently converting each of the data storage registers in the sequence of data storage registers in the sequence of data storage registers defined by the protect address from an electrically erasable programmable read only memory data storage register to a read only data storage register.

2. An electrically erasable programmable read only memory (EEPROM) device that includes a memory array comprising a plurality of electrically erasable programmable read only memory data storage registers for storing data, each data storage register having a corresponding access address associated therewith, the access addresses defining the data storage registers sequentially from an initial data storage register to a final data storage register, the EEPROM device further including means responsive to a read access address for reading data stored in a data storage register corresponding to the read access address, means responsive to an erase access address for electrically erasing data stored in a data storage register corresponding to the erase access address, and means responsive to a write access address for altering data stored in a data storage register corresponding to the write access address, the EEPROM device further comprising:

(a) an instruction register that receives a binary instruction that specifies an access address as a selected write access address;

(b) a data shift register that receives data to be written into a data storage register corresponding to the selected write access address;

(c) write means responsive to receipt of data by the data shift register for transferring data from the data shift register to the data storage register having an access address corresponding to the write access if write access to the data storage register has been enabled;

(d) a programmable memory protect register that stores the access address of a selected data storage register as a protect address, the protect address defining a sequence of data storage registers having addresses equal to or greater than the address of the selected data storage register;

(e) address decoder means responsive to receipt of a write enable signal and of the selected write access address for enabling write access to a data storage register having an access address corresponding to the selected write access address;

(f) compare/enable means for comparing the selected write access address and the protect address and for providing the write enable signal to the address decoder means only if the data storage register corresponding to the selected write access address is not within the sequence of data storage registers defined by the protect address; and

(g) means for permanently locking the protect address into the memory protect register thereby permanently converting each of the data storage registers in the sequence of data storage registers defined by the protect address from an electrically erasable programmable read only memory data storage register to a read only data storage register.