High speed latching circuit with level shift output circuits
First Claim
1. A latching circuit comprising:
- a first NAND gate having a first input end receiving a first input signal, a second input end receiving an enable signal and an output end, a second NAND gate having a first input end receiving a second input signal complementary to said first input signal, a second input end receiving said enable signal and an output end, each of said first and second NAND gates including first and second transistors connected in series between the output end thereof and a first voltage terminal and having gates coupled to the first and second input ends thereof, respectively, and a load element coupled between the output end thereof and a second voltage terminal, a first level shift circuit having an input end connected to the output end of said first NAND gate and an output end, a second level shift circuit having an input end connected to the output end of said second NAND gate and an output end, a third level shift circuit having an input end connected to the output end of said first NAND gate and an output end, a fourth level shift circuit having an input end connected to the output end of said second NAND gate and an output end, a first feedback transistor having a current path connected between the output end of said first NAND gate and said first voltage terminal and a gate, a second feedback transistor having a current path connected between the output end of said second NAND gate and said first voltage terminal and a gate, means for connecting the output end of said third level shift circuit to the gate of said second feedback transistor, means for connecting the output end of said fourth level shift circuit to the gate of said first feedback transistor, a first output terminal coupled to the output end of said first level shift circuit without connection to the output end of said third level shift circuit, and a second output terminal coupled to the output end of said second level shift circuit without connection to the output end of said fourth level shift circuit.
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Accused Products
Abstract
For prompt response to an alternation of input signal, a latching circuit comprises two NAND gates each responsive to the input signal or the inverse thereof as well as an enable signal to produce an output signal or the inverse thereof, two level shifting circuits operative to shift the output signal and the inverse thereof in voltage level, and the controller providing a voltage level to partially define the shifting range of the output signal, and each of the level shifting circuits has a capacitor and two level shifters connected to the capacitor and the controller, respectively, so that the controller has no affection of the capacitor, thereby allowing the latching operation to be improved in speed.
18 Citations
7 Claims
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1. A latching circuit comprising:
a first NAND gate having a first input end receiving a first input signal, a second input end receiving an enable signal and an output end, a second NAND gate having a first input end receiving a second input signal complementary to said first input signal, a second input end receiving said enable signal and an output end, each of said first and second NAND gates including first and second transistors connected in series between the output end thereof and a first voltage terminal and having gates coupled to the first and second input ends thereof, respectively, and a load element coupled between the output end thereof and a second voltage terminal, a first level shift circuit having an input end connected to the output end of said first NAND gate and an output end, a second level shift circuit having an input end connected to the output end of said second NAND gate and an output end, a third level shift circuit having an input end connected to the output end of said first NAND gate and an output end, a fourth level shift circuit having an input end connected to the output end of said second NAND gate and an output end, a first feedback transistor having a current path connected between the output end of said first NAND gate and said first voltage terminal and a gate, a second feedback transistor having a current path connected between the output end of said second NAND gate and said first voltage terminal and a gate, means for connecting the output end of said third level shift circuit to the gate of said second feedback transistor, means for connecting the output end of said fourth level shift circuit to the gate of said first feedback transistor, a first output terminal coupled to the output end of said first level shift circuit without connection to the output end of said third level shift circuit, and a second output terminal coupled to the output end of said second level shift circuit without connection to the output end of said fourth level shift circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
Specification