Circuit technique for cancelling non-linear capacitor-induced harmonic distortion

• US 4,999,585 A
• Filed: 11/06/1989
• Issued: 03/12/1991
• Est. Priority Date: 11/06/1989
• Status: Expired due to Term

• Current Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Original Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Inventors: Kalthoff, Timothy V., Burt, Rodney T., Stitt, R. Mark II, Heisley, David A.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/432,544
• Time in Patent Office: 491 Days
• Field of Search: 330/149, 330/288, 330/295, 330/307, 330/311, 330/257, 330/260
• US Class Current: 330/149
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications

Abstract

Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor. The second transistor produces a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the input voltage. A current mirror receives a collector current of the second transistor. The current mirror produces in the second conductor a correction signal substantially equal and opposite to the first non-linear current.

Claims

1. A method for reducing harmonic distortion in an amplifier including a first transistor having a first non-linear collector-to-substrate capacitance, the method comprising the steps of:

(a) applying a small signal input voltage to a first conductor coupled to a base of the first transistor and to the base of a second transistor, the second transistor having a second non-linear collector-to-substrate capacitance;

(b) producing a first variation in a collector voltage of the first transistor and a second variation in a collector voltage of the second transistor in response to the input voltage, and producing a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the first variation and a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the second variation;

(c) causing the first non-linear current to flow in a second conductor connected to the collector of the first transistor;

(d) causing the second non-linear current to flow in a control conductor of a current mirror, and operating the current mirror to produce a correction current in an output conductor of the current mirror in response to the second non-linear current;

(e) causing the correction current to also flow in the second conductor and thereby cancel at least a portion of the first non-linear current therein, thereby reducing harmonic distortion due to the first non-linear collector-to-substrate capacitance.

2. The method of claim 1 including causing a collector current of the second transistor to flow in the control conductor of the current mirror, and causing the collector current of the second transistor to be small compared to a collector current of the first transistor.

3. The method of claim 2 including causing a first constant current to flow through the emitter and collector of the first transistor, the second conductor, and a first load device, to thereby develop the output voltage across the first load device.

4. The method of claim 1 including causing a collector-substrate junction area of the first transistor to be a first factor times a collector-substrate junction area of the second transistor, and causing the correction current flowing through the output conductor of the current mirror to be the first factor times the second non-linear current to cause the correction current to be equal and opposite to the first non-linear current in the first conductor.

5. The method of claim 4 including using a first cascode-connected transistor coupled between the second conductor and the collector of the first transistor to maintain a constant base-to-collector voltage on the first transistor, and using a second cascode-connected transistor coupled between the control conductor of the current mirror and the collector of the second transistor to maintain a constant base-to-collector voltage on the second transistor, to thereby reduce non-linearities in the output voltage due to non-linearities in collector-base capacitances of the first and second transistors.

6. Circuitry for reducing harmonic distortion in an amplifier including a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier, the first transistor producing a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage, the circuitry comprising in combination:

(a) a second transistor having a second non-linear collector-to-substrate capacitance, a second current source coupled to an emitter of the second transistor, the first conductor being coupled to apply the input voltage to a base of the second transistor;

(b) a current mirror having a current control conductor and a current output conductor, the current control conductor being coupled to receive a collector current of the second transistor, and the current output conductor being coupled to the second conductor, the second transistor producing a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the input voltage,

the current mirror producing in the second conductor a correction signal substantially equal and opposite to the first non-linear current, in response to the second non-linear current, thereby substantially reducing harmonic distortion produced by the first non-linear collector-to-substrate capacitance.

7. The circuitry of claim 6 wherein the first load device includes a constant current source coupled between a first supply voltage conductor and the second conductor.

8. The circuitry of claim 7 wherein the first and second transistors are NPN transistors, and wherein the current mirror includes a PNP control transistor having an emitter coupled to the first supply voltage conductor and a collector coupled to the collector of the second transistor, and a PNP output transistor having its base coupled to the base and collector of the PNP control transistor and having its collector coupled to the second conductor.

9. The circuitry of claim 8 including a differential amplifier having a non-inverting input coupled to the collector of the PNP control transistor and an inverting input coupled to the second conductor, and an output coupled to one electrode of a feedback resistor, another electrode of which is coupled to one electrode of a gain resistor, another electode of which is coupled to a second supply voltage conductor, a junction between the feedback resistor and the gain resistor being coupled to the emitter of the first transistor.

10. The circuitry of claim 8 including a first NPN cascode transistor coupled between the second conductor and the collector of the first transistor, and a second NPN cascode transistor coupled between the collector of the PNP control transistor and the collector of the second transistor, the bases of the first and second NPN cascode transistors being coupled to an emitter of an emitter follower transistor having a base coupled to the first conductor.

11. The circuitry of claim 6 wherein the first and second transistors are NPN transistors, the first load device being a constant current source, a second constant current source being coupled between the collector of the second transistor and a first positive supply voltage conductor and functioning as a second load device, the current mirror including an NPN control transistor having a collector coupled to the collector of the second transistor and to a non-inverting input of a differential amplifier, and an NPN current output transistor having an emitter coupled to the emitter of the control transistor, a base of the NPN current output transistor being connected to a base and collector of the NPN control transistor, a PNP emitter follower transistor having its base coupled to the first conductor, the emitter of the PNP emitter follower transistor being coupled to emitters of the NPN control transistor and the NPN current output transistor, an inverting input of the differential amplifier being coupled to the second conductor, an output of the differential amplifier being connected to one terminal of a feedback resistor, another terminal of which is connected to one terminal of a gain resistor, another terminal of which is connected to a second supply voltage conductor, the emitter of the first transistor being coupled to a junction between the feedback resistor and the gain resistor.

12. The circuitry of claim 6 wherein the current mirror produces an output current which is a first factor times a current in the emitter of the current control conductor thereof, and the first non-linear collector-to-substrate capacitance is equal to the first factor times the second non-linear collector-to-substrate capacitance.

13. The circuitry of claim 12 wherein the emitter current of the second transistor is substantially smaller than the emitter current of the first transistor divided by the first factor.

14. A method for reducing effects of a first parasitic capacitance of a first transistor in an amplifier, the method comprising the steps of:

(a) applying a small signal input voltage to a first conductor coupled to a control electrode of the first transistor and to a control electrode of a second transistor, the second transistor having a second parasitic capacitance;

(b) producing a first variation in a current-carrying electrode voltage of the first transistor and a second variation in a current-carrying electrode voltage of the second transistor in response to the input voltage, and producing a first parasitic current in the first parasitic capacitance in response to the first variation and a second parasitic current in the second parasitic capacitance in response to the second variation;

(c) causing the first parasitic current to flow in a second conductor connected to a current-carrying electrode of the first transistor;

(d) causing the second parasitic current to flow in a control conductor of a current mirror, and operating the current mirror to produce a correction current in an output conductor of the current mirror in response to the second parasitic current

(e) causing the correction current to also flow in the second conductor and thereby cancel at least a portion of the first parasitic current therein, thereby reducing the effects of the first parasitic capacitance.

15. An instrumentation amplifier having low harmonic distortion, comprising in combination:

(a) a first amplifier;

(b) a second amplifier;

(c) a difference amplifier having a first input coupled to an output of the first amplifier and a second input coupled to an output of the second amplifier, wherein each of the first and second amplifiers includes circuitry for reducing harmonic distortion in an amplifier including

i. a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier, the first transistor producing a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage,

ii. a second transistor having a second non-linear collector-to-substrate capacitance, a second current source coupled to an emitter of the second transistor, the first conductor being coupled to apply the input voltage to a base of the second transistor;

iii. a current mirror having a current control conductor and a current output conductor, the current control conductor being coupled to receive a collector current of the second transistor, and the current output conductor being coupled to the second conductor, the second transistor producing a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the input voltage,

the current mirror producing in the second conductor a correction signal substantially equal and opposite to the first non-linear current, in response to the second non-linear current, thereby substantially reducing harmonic distortion produced by the first non-linear collector-to-substrate capacitance.