High speed complementary field effect transistor logic circuits

• US 5,001,367 A
• Filed: 04/14/1989
• Issued: 03/19/1991
• Est. Priority Date: 04/14/1989
• Status: Expired due to Term

• Current Assignee: Technology Properties Limited LLC
• Original Assignee: Thunderbird Technologies Incorporated
• Inventors: Vinal, Albert W.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US07/338,280
• Time in Patent Office: 704 Days
• Field of Search: 307/443, 307/448, 307/450, 307/451, 307/481, 307/482, 307/571, 307/585, 307/579, 307/475, 307/542, 307/449, 307/279, 307/542.1
• US Class Current: 326/108
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/09485 with active depletion transistors

Abstract

A high speed, high density, low power dissipation all parallel FET logic circuit includes a driving stage having a plurality of parallel FETs of a first conductivity type for receiving logic input signals and a load FET of second conductivity type connected to the common output of the driving stage. A complementary FET inverter including serially connected FETs of first and second conductivity type is connected to the common output and the load FET. According to the invention the voltage transfer function of the complementary inverter is skewed so that the product of the carrier mobility and the ratio of channel width to length of the inverter FET of the first conductivity type is made substantially greater than the product of the carrier mobility and the ratio of channel width to length of the inverter FET of the second conductivity type. By skewing the voltage transfer function of the complementary inverter the voltage lift-off interval is dramatically decreased, thereby improving the speed. AND and OR circuits and combined AND-OR circuits may be provided, having true and complement outputs. A multigate serial load transistor may further reduce power consumption.

Claims

1. A field effect transistor (FET) logic circuit comprising:

a driving stage including at least one FET of a first conductivity type, having at least one control electrode for receiving logic input signals, the at least one driving stage FET being connected between a common output and a first potential level;

a load FET of second conductivity type, connected between a second potential level and said common output; and

a complementary FET inverter comprising an FET of said first conductivity type and an FET of said second conductivity type, serially connected between said first and second potential levels, the output of said complementary inverter being connected to the control electrode of said load FET, the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said first conductivity type being substantially greater than the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said second conductivity type.

2. The FET logic circuit of claim 1 wherein said logic circuit is an OR circuit with said first conductivity type being N-type and said second conductivity type being P-type.

3. The FET logic circuit of claim 1 wherein said logic circuit is an AND circuit with said first conductivity type being P-type and said second conductivity type being N-type.

4. The FET logic gate of claim 1 wherein said driving stage FETs are enhancement type FETs.

5. The FET logic gate of claim 4 wherein said driving stage FETs are enhancement type FETs having an induced channel.

6. The FET logic gate of claim 1 wherein the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said first conductivity type is four times the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said second conductivity type.

7. The FET logic gate of claim 1 wherein said load FET is a depletion mode FET.

8. The FET logic gate of claim 1 wherein said load FET is slightly conductive when the control electrode thereof is near said second potential level.

9. The FET logic gate of claim 1 wherein said load FET is highly conductive when the control electrode thereof is near said first potential level.

10. The FET logic gate of claim 1 further comprising a second load FET of said second conductivity type, connected between said second potential level and said common output, the control electrode of said second load FET being connected to one of the control electrodes of said driving stage FETs.

11. The FET logic gate of claim 1 wherein the product of the carrier mobility and the ratio of channel width to length of said driving stage FETs is greater than the product of carrier mobility and the ratio of channel width to length of said load FET.

16. The FET logic gate of claim 1 wherein at least one driving stage FET comprises a driving stage FET having a plurality of control electrodes for receiving logic input signals.

17. The FET logic gate of claim 16 wherein said driving stage FET having a plurality of control electrodes comprises a multigate Fermi-Threshold FET.

18. The FET logic gate of claim 1 wherein at least two driving stage FETs are connected in parallel with each other between said common output and said first potential level.

19. The FET logic gate of claim 1 wherein at least two driving stage FETs are connected in series between said common output and said first potential level.

20. The FET logic gate of claim 1 wherein at least three driving stage FETs are connected in a series/parallel configuration between said common output and said first potential level.

12. A field effect transistor (FET) logic circuit comprising:

a driving stage including at least one FET of a first conductivity type, having at least one control electrode for receiving logic input signals, the at least one driving stage FET being connected between a common output and a first potential level;

a load FET of second conductivity type, connected between a second potential level and said common output;

a complementary FET inverter comprising an FET of said first conductivity type and an FET of said second conductivity type, serially connected between said first and second potential levels, the output of said complementary inverter being connected to the control electrode of said load FET, the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said first conductivity type being substantially greater than the product of the carrier mobility and the ratio of channel width to length of the inverter FET of said second conductivity type;

a second load FET of said conductivity type, connected between said second potential and said common output; and

a second complementary FET inverter comprising an FET of said first conductivity type and an FET of said second conductivity type, serially connected between said first and second potential levels, the output of said second complementary FET inverter being connected to the control electrode of said second load FET.

13. The FET logic gate of claim 12 wherein the product of the carrier mobility and the ratio of channel width to length of the second complementary inverter FET of said first conductivity type is equal to the product of the carrier mobility and the ratio of channel width to length of the second complementary inverter FET of said second conductivity type.

14. The FET logic gate of claim 12 wherein said second load FET comprises an FET having a plurality of gate electrodes, a respective one of said plurality of second load FET gate electrodes being connected to a respective one of the control electrodes of said driving stage FETs.

15. The FET logic gate of claim 14 wherein said second load FET is a multigate Fermi-Threshold FET.