×

DAC current source bias equalization topology

  • US 5,001,484 A
  • Filed: 05/08/1990
  • Issued: 03/19/1991
  • Est. Priority Date: 05/08/1990
  • Status: Expired due to Fees
First Claim
Patent Images

1. A digital-to-analog converter current source having M+N number of bits, comprising:

  • a dimension-scaled weighted array of N current sources that conduct N first scaled currents, the array including N first transistors connected to different ones of N second transistors, one of the N first transistors having a dimension w; and

    a dimension-scaled weighted cascode current divider comprised of M current sources, the current divider including M third transistors that conduct M second scaled currents which are summed at a node, the node being connected to a master current transistor that conducts a current Is having a magnitude, the master current transistor having a dimension w, the bias of the N first transistors being tied to the node, whereby relative magnitudes of the N first scaled currents remain in correct proportion to relative magnitudes of the M second scaled currents in spite of changes in the magnitude of current Is.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×