CMOS integrated circuit with EEPROM and method of manufacture

• US 5,014,098 A
• Filed: 02/26/1990
• Issued: 05/07/1991
• Est. Priority Date: 02/26/1990
• Status: Expired due to Term

• Current Assignee: Bewes Assets LLC (Intellectual Ventures LLC)
• Original Assignee: Delco Electronics LLC
• Inventors: Schlais, John R., Rusch, Randy A., Simacek, Thomas H.
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Hung, Dang Xuan
• Application Number:
  US07/484,829
• Time in Patent Office: 435 Days
• Field of Search: 357/23.5, 357/42, 357/23.3
• US Class Current: 257/316
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors. Additional steps are inserted in the standard CMOS process to form the EEPROM. The additional steps are inserted in such a manner so as not to adversely affect the operating characteristics of the resulting MOS transistors. For this purpose, any additional steps for forming the EEPROM which are carried out at a temperature of greater than 900° C. are done so before the gate silicon dioxide layer of the MOS transistors is formed, and any further steps of forming the EEPROM are carried out at temperatures no greater than 900° C.

Claims

1. An integrated circuit comprising:

a substrate of a semiconductor material having a surface;

an MOS transistor in said substrate at said surface and having a gate electrode with a feature size of no greater than about two microns and having a maximum voltage capability; and

an EEPROM in said substrate at said surface, said EEPROM being capable of being programmed at voltages which are compatible with the maximum voltage capability of the MOS transistor, and the EEPROM having a control gate and a floating gate with a ratio of capacitance of the floating gate to control gate to capacitance of the floating gate to substrate of at least about two.

2. The integrated circuit of claim 1 wherein the EEPROM comprises a floating gate and a control gate over and insulated from the floating gate, and the floating gate and control gate each have large overlapping areas laterally disposed from a channel area of the EEPROM to provide a large capacitance therebetween for applying and removing charge from said control gate.

3. The integrated circuit of claim 2 wherein the EEPROM further comprises a layer of silicon dioxide on the surface of the substrate, an opening in said silicon dioxide layer, a tunnel oxide layer thinner than the silicon dioxide layer on the substrate surface in said opening, and the floating gate is on the silicon oxide layer and on the tunnel oxide layer in the opening.

4. The integrated circuit of claim 3 wherein the ratio of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance is high enough to allow a voltage level for a programming voltage which is within the maximum voltage capability of the MOS transistor.

5. The integrated circuit of claim 4 wherein the MOS transistor is but one of many MOS transistors on said surface having a gate electrode feature size of up to about two microns, and none of the characteristics of the MOS transistors are compromised because of the concurrent presence of the EEPROM, effective to allow the MOS transistors to operate at high speed.

6. An integrated circuit comprising:

a substrate of a semiconductor material having a surface;

a pair of complementary MOS transistors in said substrate at said surface with each having a gate electrode feature size no greater than about two microns and also having a maximum voltage capability; and

an EEPROM in said substrate at said surface, said EEPROM being capable of being programmed at voltages which are compatible with the maximum voltage capability of the complementary MOS transistors, and the EEPROM having a control gate and a floating gate with a ratio of capacitance of the floating gate to control gate to capacitance of a floating gate to substrate of at least about two.

7. An integrated circuit comprising:

a substrate of a semiconductor material having a surface;

a plurality of complementary MOS transistors in said substrate at said surface with each using two micron or less design having a gate electrode feature size no greater than about two microns and also having a reverse break-down voltage and a maximum voltage capability; and

a plurality of EEPROM units in said substrate at said surface, each said EEPROM unit capable of being programmed at voltages which are within the reverse break-down voltage of the complementary MOS transistors, and each EEPROM unit has a control gate and a floating gate with a ratio of capacitance of the floating gate to control gate to capacitance of a floating gate to substrate of at least about two, effective to provide an IC with high-speed complementary MOS transistor logic and also with EEPROM units that are programmable with voltages compatible with the maximum voltage capability of the high-speed complementary MOS transistors.