Symmetrical variable impedance apparatus employing MOS transistors

• US 5,021,747 A
• Filed: 11/22/1989
• Issued: 06/04/1991
• Est. Priority Date: 11/22/1989
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Semiconductor Patents, Inc.
• Inventors: Isham, Robert H., Zazzu, Victor
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/440,187
• Time in Patent Office: 559 Days
• Field of Search: 330/284, 307/552, 307/564, 307/568, 333/81 R
• US Class Current: 330/284
• CPC Class Codes: H03G 1/007 using FET type devices
• CPC Class Codes: H03G 3/3015 using diodes or transistors

Abstract

A variable impedance element which is utilized to shunt a signal and control the amplitude of the signal utilizes a P-MOS and an N-MOS transistor operated in parallel. Separate control voltages are applied to each device in a direction to lower the impedance of the device with an increase in the peak to peak voltage of the input signal. Thus, by controlling each of the separate shunted transistors from separate peak detectors and according to the polarity of the signal voltage, each transistor will operate somewhat independent from the other to therefore provide accurate gain control and a symmetrical impedance variation.

Claims

1. Apparatus for providing a linear controllable impedance between first and second terminals comprising:

a P-channel field effect transistor (FET) and an N-channel FET, each FET having a source to drain path and a gate electrode with the source to drain path of each FET connected between said first and second terminals;

first means, including first comparator means responsive to the signal at said first terminal having a first polarity and being greater than a given amplitude, coupled to the gate electrode of said P-FET for applying a first control signal to said gate electrode of said P-FET for controlling the impedance of said P-FET, and

second means, including a second comparator means responsive to the signal at said first terminal having a polarity opposite said first polarity and being greater than a given amplitude, coupled to the gate electode of said N-FET for applying a second control signal to said gate electrode of said N-FET for controlling the impedance of said N-FET, to thereby provide a linear impedance between said first and second terminals.

2. The apparatus according to claim 1 wherein said P- and N-channel FETs are MOSFETs.

3. The apparatus according to claim 2 wherein said P-MOSFET and said N-MOSFET are matched devices.

4. The apparatus according to claim 1 further comprising:

means coupled to said first terminal adapted to receive an AC input signal from a source, with said second terminal coupled to a point of reference potential; and

wherein said first comparator means includes a positive peak detector means having an input coupled to said first terminal and for providing said first control signal according to the amplitude of positive peaks of said AC input signal at an output of said peak detector means and means for coupling said output of said positive detector means to said gate electrode of said P-FET; and

wherein said second comparator means includes a negative peak detector means having an input coupled to said first terminal and for providing said second control signal according to the amplitude of negative peaks of said AC input signal at an output of said negative peak detector means and means for coupling said output of said negative peak detector means to said gate electrode of said N-FET, to thereby vary the impedance of said source to drain path of said P-FET according to the magnitude of positive peaks of said signal and to vary the impedance of said source to drain path of said N-FET according to the magnitude of negative peaks of said signal, to cause the impedance across said first and second terminals to vary symmetrically as controlled by said positive and negative peak detector means.

5. The apparatus according to claim 4 wherein said positive and negative peak detector means are further responsive to reference levels to cause said detector means to provide said output when said AC input signal peaks exceeds a value indicative of said reference levels.

6. The apparatus according to claim 4 wherein said positive and negative peak detector means includes positive and negative comparators each operative to provide said control signal when said associated peaks exceed a comparator reference level.

7. An apparatus for use in a gain controlled system of the type including a source of AC signals for providing a signal output having specified positive and negative peaks with the signal output of said source directed through a first impedance to an output terminal, with said output terminal shunted to a point of reference potential by a variable shunt impedance, with the value of said shunt impedance controlled by peak detector means to vary said shunt impedance according to a control output signal from said peak detector means with said peak detector means having an input coupled to said output terminal to provide said control output signal according to the magnitude of said signal output form said AC source, the improvement therewith comprising a symmetrical variable impedance apparatus for providing said variable shunt impedance, comprising:

first and second FET devices of opposite conductivity type and having their source to drain paths connected in parallel and shunting said output terminal to said point of reference potential, and each having a gate control electrode and wherein said peak detector means includes a positive peak detector means having an input coupled to said output terminal for receiving said AC signal and for providing at an output a first control signal indicative of the magnitude of positive peaks associated with said AC signal and means for coupling said positive peak detector output to said gate electrode of said first FET device to vary the impedance of said drain to source path of said first device according to said positive peak detection, a negative peak detector means having an input coupled to said output terminal for receiving said AC signal and for providing at an output a second control signal indicative of the magnitude of negative peaks associated with said AC signal and means for coupling said negative peak detector output to said gate electrode of said second FET device to vary the impedance of said drain to source path of said second device according to said negative peak detection, whereby said first and second FETs operate to symmetrically vary the impedance between said output terminal and said point of reference potential according to the impedances of said first and second FETs as varied by said first and second control signals.

8. The apparatus according to claim 7 wherein said first FET device is a P-MOSFET and said second FET device is an N-MOSFET.

9. The apparatus according to claim 8 wherein said P- and N-MOSFETs are matched devices.

10. The apparatus according to claim 7 wherein said positive and negative peak detector means each include a separate comparator means operative to provide an output when a reference input comparison level is exceeded to thereby provide said associated control signal when said comparison level is exceeded.

11. The apparatus according to claim 7 further including an amplifier having an input coupled to said output terminal for providing an amplified version of said AC signal at an amplifier output terminal, with said amplifier output terminal coupled to said input of said positive and negative peak detector means.

12. A gain control apparatus for controlling the gain of an AC signal by providing a controlled linear impedance which varies as a function of the magnitude of said AC signal, comprising:

first and second MOSFETs of opposite conductivity types and having their source to drain paths connected in parallel between an input terminal and a point of reference potential;

means coupled to said input terminal for applying said AC signal thereto;

an amplifier having an input coupled to said input terminal and an output terminal for providing an amplified version of said AC signal;

a first comparator means having an input coupled to said amplifier output terminal and a reference input adapted to receive a first reference potential, said comparator operative to respond to the magnitudes of positive peaks of said AC signal to provide at an output a first control signal when positive peaks of said AC signal exceed said first reference potential, with the output of said first comparator means coupled to the gate electrode of said first MOSFET via a first unidirectional conducting device, with the terminal of said unidirectional device as coupled to said gate electrode of said first MOSFET directed to said point of reference potential via a first capacitor;

a first current source coupled to said gate electrode of said first MOSFET and operative to divert current from said first capacitor to render said first MOSFET in a non-conducting state for positive peak levels below a given value, wherein when said positive peaks of said AC signal are above said first reference potential said first comparator means provides an output signal causing said capacitor to charge via said unidirectional device towards the level of said output signal to thereby cause said first FET to conduct to thereby reduce the impedance between said source to drain and thereby decreasing the AC signal applied to said input terminal in a direction to maintain a constant level AC signal at said output terminal during the positive peaks of said AC signal;

a second comparator means having one input coupled to said amplifier output terminal and a reference input adapted to receive a second reference potential, said second comparator operative to respond to the magnitudes of negative peaks of said AC signal to provide at an output a second control signal when negative peaks of said AC signal exceed said second reference potential, with the output of said second comparator means coupled to the gate electrode of said second MOSFET via a second unidirectional conducting device of opposite polarity to said first device, with the terminal of said second unidirectional device as coupled to said gate electrode of said second MOSFET directed to said point of reference potential via a second capacitor;

a second current source coupled to said gate electrode of said second MOSFET and operative to divert current from said second capacitor to render said second MOSFET in a non-conducting state for negative peak levels below a given value, wherein when said negative peaks of said AC signal are above said second reference potential said second comparator provides an output signal causing said second capacitor to charge via said second unipolar device towards the level of said output signal to thereby cause said second FET to conduct to thereby reduce the impedance between said source to drain and thereby decreasing the AC signal applied to said input terminal in a direction to maintain a constant level signal at said output terminal during said negative peaks of said AC signal;

whereby the impedance afforded by said first and second MOSFETS at said input terminal is linearly controlled by varying the source to drain impedance of said first and second MOSFETs.

13. The gain control apparatus according to claim 12 wherein said first MOSFET is a P-MOS device, with said second MOSFET being an N-MOS.

14. The gain control apparatus according to claim 13 wherein MOSFETs are matched devices.

15. The gain control apparatus according to claim 12 wherein said first and second unipolar devices are MOSFETs, biased to conduct current in a unidirectional manner.

16. The gain control apparatus according to claim 12 wherein said means coupled to said input terminal includes a capacitor in series with a resistor, with said capacitor operative to block DC from being applied to said input terminal by said AC signal.

17. The gain control apparatus according to claim 12 wherein said first reference potential is positive with respect to said second reference potential.

18. The gain control apparatus according to claim 12 further including a third MOSFET in parallel with said first MOSFET and of the same polarity and having the gate electrode of said third MOSFET coupled to the gate electrode of said first MOSFET, and a fourth MOSFET in parallel with said second MOSFET and of the same polarity and having the gate electrode of said fourth MOSFET coupled to the gate electrode of said second MOSFET.

19. The gain control apparatus according to claim 12 further including a voltage divider coupled between a source of operating potential and a point of reference potential and operative to provide said first and second reference potentials at first and second terminals of said voltage divider.

20. The gain control apparatus according to claim 12 wherein said first and second capacitors are equal in value.