Power saving arrangement and power saving method

• US 5,027,428 A
• Filed: 09/05/1989
• Issued: 06/25/1991
• Est. Priority Date: 09/07/1988
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Ishiguro, Kazuhisa, Sekiguchi, Yutaka
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Pham, Chi H.
• Application Number:
  US07/403,101
• Time in Patent Office: 658 Days
• Field of Search: 455/127, 455/226, 455/343, 455/67
• US Class Current: 340/7.35
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A power saving arrangement for use in a handset unit which communicates with a base unit in response to the detection of an ID signal leading data signal, which are produced from the base unit, includes a processing circuit for receiving and processing the ID signal and data signal, and a detecting circuit, connected to the processing circuit, for detecting the ID signal and data signal. A CPU controls the power supply such that, under the first standby mode a reduced power is supplied to the processing circuit, and no power to the detecting circuit. Under the second standby mode as established when the detected level of the received signal exceeds a predetermined level, the reduced power is supplied to the processing circuit means and also to the detecting circuit means. Under the use mode as established when the detected ID signal has a predetermined pattern, full power is supplied to the processing circuit and also to the detecting circuit.

Claims

1. A power saving arrangement for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit and received by said subsidiary unit, said power saving arrangement comprising:

power control circuit for selectively producing a full power and a reduced power;

a processing circuit means for receiving and processing said data signal when the full power is applied thereto, and for detecting the level of the received signal when the reduced electric power is applied thereto;

detecting circuit connected to said processing circuit means for detecting said data signal when the full power is applied thereto, and for detecting only said ID signal when the reduced power is applied thereto;

first switching means for making and breaking a power supply path to said detecting circuit means from said power control circuit; and

control means responsive to a signal representing the level of the received signal obtained from said processing means and also to said ID signal obtained from said detecting circuit means for controlling said power control circuit and said first switching means to establish either one of first standby mode, second standby mode and use mode such that;

under the first standby mode, said first switching means breaks the power supply to said detecting circuit means and, at the same time, said power control circuit produces the reduced power to said processing circuit means, ready to detect the level of the received signal;

under the second standby mode as established when said control means detects that the received signal level exceeds a predetermined level, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the reduced power to said processing circuit means and also to said detecting circuit means, ready to detect and read the pattern of said ID signal; and

under the use mode as established when said control means detects that said ID signal has a predetermined pattern, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the full power to said processing circuit means and also to said detecting circuit means, ready to detect and read said data signal.

2. A power saving arrangement as claimed in claim 1, wherein said processing circuit means comprises a signal strength detecting circuit for detecting the signal level of the received signal.

3. A power saving arrangement as claimed in claim 2, further comprising a second switching means which operates synchronizingly with said first switching means for making and breaking the power supply partially to said signal strength detecting circuit.

4. A power saving arrangement as claimed in claim 1, wherein said processing circuit means comprises a first stage amplifier.

5. A power saving arrangement as claimed in claim 1, wherein said detecting circuit means comprises a second stage amplifier and a detector/modulator circuit.

6. A power saving arrangement as claimed in claim 1, wherein said control means comprises a CPU.

7. A power saving arrangement as claimed in claim 1, wherein said power control circuit comprises an operation control for producing said full power or said reduced power.

8. A power saving arrangement as claimed in claim 7, wherein said operation control produces power intermittently thereby generating said reduced power.

9. A power saving method for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit, said subsidiary unit having a processing circuit means for receiving and processing said ID signal and data signal, control means for generating a control signal in response to output signals from said processing circuit means and said detecting circuit means, and power control means for generating either one of a reduced power signal and a full power signal in response to said control signal, the power saving method comprising the steps of:

providing a reduced power to said processing circuit means and providing no power to said detecting circuit means when said ID signal and data signal are not present, being ready to detect the level of the received signal by said processing circuit means;

providing said reduced power to said processing circuit means and also to said detecting circuit means from power control means when the detected received signal level exceeds a predetermined level and being ready to detect the pattern of said ID signal by said detecting circuit means; and

providing full power to said processing circuit means from power control means when the detected ID signal pattern is identical to a predetermined pattern and being ready to detect and reproduce the data signal.

10. A power saving method as claimed in claim 9, wherein said reduced power is produced by intermittently generating the power.