High speed logic and memory family using ring segment buffer
DCFirst Claim
1. An integrated circuit Ring Segment Buffer for driving a capacitive load, comprising:
- a plurality of serially connected complementary field effect transistor inverter stages, each of said complementary field effect transistor inverter stages comprising a serially connected N-channel field effect transistor and P-channel field effect transistor, the N-channel and P-channel field effect transistors having predetermined channel widths and channel lengths, each of said complementary field effect transistor inverter stages having an input and an output, with the output of an immediately preceding inverter stage being connected to the input of an immediately succeeding inverter stage, and the output of the last inverter stage being connected to the capacitive load;
the N-channel field effect transistor in each inverter stage having a channel width which is less than a predetermined factor times the width of the N-channel of the immediately preceding inverter stage, whereby said Ring Segment Buffer drives said capacitive load at high speed.
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Abstract
A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET in each inverter stage has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages. For large capacitive loads, the last stage of the Ring Segment Buffer may be replaced by a bipolar transistor-FET driver in which minority carrier lifetime controlled bipolar transistors are used.
The Buffer Cell Logic and Delay Storage technology of the present invention may operate at speeds of 300 megahertz or more using conventional semiconductor fabrication processes in which conventional CMOS logic and memory technology operates at 70 megahertz or less. A fourfold speed improvement is thereby obtained.
30 Citations
90 Claims
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1. An integrated circuit Ring Segment Buffer for driving a capacitive load, comprising:
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a plurality of serially connected complementary field effect transistor inverter stages, each of said complementary field effect transistor inverter stages comprising a serially connected N-channel field effect transistor and P-channel field effect transistor, the N-channel and P-channel field effect transistors having predetermined channel widths and channel lengths, each of said complementary field effect transistor inverter stages having an input and an output, with the output of an immediately preceding inverter stage being connected to the input of an immediately succeeding inverter stage, and the output of the last inverter stage being connected to the capacitive load; the N-channel field effect transistor in each inverter stage having a channel width which is less than a predetermined factor times the width of the N-channel of the immediately preceding inverter stage, whereby said Ring Segment Buffer drives said capacitive load at high speed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An integrated circuit Buffer Cell Logic chip comprising:
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a plurality of interconnected logic gates, each having a predetermined number of logic gate inputs and a logic gate output, the logic gate output of each logic gate driving an associated effective capacitance, for performing a predetermined logic function; a plurality of buffers, each having an input and an output, a respective one of said plurality of buffers being associated with a respective one of said plurality of logic gates, the input of each buffer being connected to the logic output of the associated logic gate, the output of each buffer being connected to the associated effective capacitance; each of said buffers being configured to drive the associated effective capacitance at a predetermined Buffer Cell Logic chip speed; whereby each of the logic gates in said integrated circuit logic chip performs said predetermined logic function at said predetermined Buffer Cell Logic chip speed, notwithstanding the associated effective capacitance for each logic gate. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
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57. A Delay Storage cell comprising:
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a memory cell having an input and an output, for storing therein a data value from said input and for providing a stored data value to said output; and a Delay Ring Segment Buffer coupled to said memory cell output, said Delay Ring Segment Buffer comprising a plurality of serially connected complementary field effect transistor stages, each of said complementary field effect transistor inverter stages comprising a serially connected N-channel field effect transistor and P-channel field effect transistor, the N-channel and P-channel field effect transistors having predetermined channel widths and channel lengths, each of said complementary field effect transistor inverter stages having an input and an output, with the output of an immediately preceding inverter stage being connected to the input of an immediately succeeding inverter stage and the output of the last inverter stage being connected to a capacitive load; each field effect transistor in the Delay Ring Segment Buffer having a predetermined channel length selected to provide a predetermined delay in said Delay Ring Segment Buffer; the N-channel field effect transistor in each inverter stage having a channel width which is less than a predetermined factor times the width of the N-channel of the immediately preceding inverter stage; whereby said Delay Storage cell stores the new input data value therein and provides the previously stored data value at the output of said Delay Ring Segment Buffer until the end of said predetermined delay. - View Dependent Claims (58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77)
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78. An integrated circuit Field Effect Transistor (FET) logic circuit comprising:
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a first plurality of FETs of a first conductivity type, each having a control electrode for receiving a logic input signal, said first plurality of FETs of a first conductivity type being connected in parallel between a first potential level and a common output; a first plurality of FETs of a second conductivity type, each having a control electrode for receiving a logic input signal, said first plurality of FETs of a second conductivity type being connected in series between a second potential level and said common output; and a first plurality of logic input signals, a respective one of which is connected to a respective one of the control electrodes of the first plurality of FETs of a first conductivity type and a respective one of the control electrodes of the first plurality of FETs of a second conductivity type; said FETs each having a channel, with the channel in each of said first plurality of FETs of a second conductivity type being said first plurality times wider than the channel in each of said first plurality of FETs of a first conductivity type;
whereby said FET logic circuit has a symmetrical transfer function at said common output. - View Dependent Claims (79)
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80. An integrated circuit bipolar transistor-field effect transistor (BIFET) driver for a capacitive load, comprising:
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a bipolar transistor comprising a base of first conductivity type and an emitter and a collector of second conductivity type, one of the collector and emitter being connected to the capacitive load; a field effect transistor comprising a source and a drain of said first conductivity type; the drain of said field effect transistor being electrically connected to the base of the bipolar transistor; the minority carrier lifetime in said base being less than 8e-9 seconds; whereby the capacitive load is driven at high speed. - View Dependent Claims (81, 82, 83, 84)
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85. An integrated bipolar transistor complementary metal oxide semiconductor (BICMOS) field effect transistor (FET) driver for a capacitive load, comprising:
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a CMOS inverter having an input and an output; a bipolar transistor complementary emitter follower having an input and an output, the output of said CMOS inverter being electrically connected to the input of said bipolar transistor complementary emitter follower, the output of said bipolar transistor complementary emitter follower being connected to said capacitive load; the minority carrier lifetime in the base regions of the bipolar transistors complementary emitter follower being less than 8e-9 seconds; whereby the capacitive load is driven at high speed. - View Dependent Claims (86, 87, 88, 89, 90)
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Specification