High speed logic and memory family using ring segment buffer

  • US 5,030,853 A
  • Filed: 03/21/1990
  • Issued: 07/09/1991
  • Est. Priority Date: 03/21/1990
  • Status: Expired due to Term
First Claim
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1. An integrated circuit Ring Segment Buffer for driving a capacitive load, comprising:

  • a plurality of serially connected complementary field effect transistor inverter stages, each of said complementary field effect transistor inverter stages comprising a serially connected N-channel field effect transistor and P-channel field effect transistor, the N-channel and P-channel field effect transistors having predetermined channel widths and channel lengths, each of said complementary field effect transistor inverter stages having an input and an output, with the output of an immediately preceding inverter stage being connected to the input of an immediately succeeding inverter stage, and the output of the last inverter stage being connected to the capacitive load;

    the N-channel field effect transistor in each inverter stage having a channel width which is less than a predetermined factor times the width of the N-channel of the immediately preceding inverter stage, whereby said Ring Segment Buffer drives said capacitive load at high speed.

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