Microprocessor controlled rate-responsive pacemaker having automatic rate response threshold adjustment

• US 5,040,534 A
• Filed: 05/30/1990
• Issued: 08/20/1991
• Est. Priority Date: 01/25/1989
• Status: Expired due to Term

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Siemens Pacesetter, Inc. (Abbott Laboratories Incorporated)
• Inventors: Poore, John W., Mann, Brian M.
• Primary Examiner(s): Jaworski, Francis
• Assistant Examiner(s): MANUEL, GEORGE C
• Application Number:
  US07/530,368
• Time in Patent Office: 447 Days
• Field of Search: 128/419 P, 128/419 PG, 128/419 PS
• US Class Current: 607/19
• CPC Class Codes: A61N 1/36542 controlled by body motion, e.g. acceleration

Abstract

A rate-responsive pacemaker which includes a conventional programmable pulse generator, a physiological sensor, and a processor is disclosed which generates heart stimulation pulses on demand, or as otherwise programmed, as controlled by a rate control signal which is derived from the physiological sensor. The physiological sensor generates a raw signal which varies as a function of some physiological parameter, such as activity level to provide some indication of whether the heart rate should increase or decrease, and hence whether the pacemaker should change the rate at which pacing pulses are provided. The processor converts the raw signal to the sensor-indicated rate signal in accordance with a selectable transfer relationship which defines the sensor-indicated rate signal as a function of a set of discrete sensor level index signals. The sensor-indicated rate signal remains at a minimum value or base rate for all sensor level index signals below a prescribed rate response threshold, with this rate response threshold being set automatically by the processor as a function of a running average of the sensor level index signals monitored over a prescribed time period.

Claims

1. In a pacemaker comprising an implantable housing;

a battery within said housing;

a pacemaker chip within said housing and connected to said battery;

a connector block attached to said housing and said pacemaker chip to which a pacemaker lead may be detachably connected, the improvement comprising;

a microprocessor chip within said housing and connected to said pacemaker chip and said battery;

memory means coupled to said microprocessor chip for storing program data which controls the operation of said microprocessor chip;

sensor means for sensing a physiological parameter and for generating a raw sensor signal as a function thereof;

sensor circuit means for generating one of a plurality of sensor level signals as a function of the average amplitude of said raw sensor signal, and for presenting said sensor level signal to said microprocessor chip;

processing means included in said microprocessor chip, said processing means responsive to the program data stored in said memory means for generating a pacing rate signal which varies in a prescribed manner as a function of the sensor level signal, said pacing rate signal being presented to said pacemaker chip; and

means, included in said pacemaker chip, for responding to said pacing rate signal in order to alter the rate at which pacing pulses are generated by said pacemaker.

2. The pacemaker of claim 1, wherein the sensor circuit means comprises means for generating one of a discrete number of sensor level signals as a function of the average amplitude of said raw sensor signal.

3. The pacemaker of claim 1, wherein the number of discrete sensor level signals is at least thirty-two.

4. The pacemaker of claim 1, wherein said prescribed manner in which said pacing rate signal varies as a function of the sensor level signal comprises a lower pacing rate limit whenever said sensor level signal is less than a low rate response threshold value, and an upper pacing rate limit whenever said sensor level signal is greater than a maximum rate response level, and one of a plurality of intermediate pacing rate values whenever said sensor level signal is between said low rate response threshold value and said maximum rate response level, there being an intermediate pacing rate value for each sensor level signal falling between said low rate response threshold value and said maximum rate response level.

5. The pacemaker of claim 4, wherein the low rate response threshold value of said sensor level signal is programmably selectable.

6. The pacemaker of claim 4, wherein said processing means of said microprocessor chip comprises:

means for monitoring and processing the sensor level signal generated by said sensor circuit means over a prescribed period of time and for generating a reference sensor signal as a result of said monitoring and processing; and

further wherein the low rate response threshold value of said sensor level signal is automatically setable by said processing means to a value derived from said reference sensor signal.

7. The pacemaker of claim 1, wherein said pacemaker chip further comprises:

means for selectively receiving said pacing rate signal from said microprocessor chip, said pacemaker chip including means for referencing a base rate pacing signal in the event said pacing rate signal is not received;

whereby the pacemaker produces stimulation pulses at a rate determined by said base rate pacing signal when said pacing rate signal is not received from said microprocessor chip, and at a rate determined by said pacing rate signal when said pacing rate signal is received from said microprocessor chip.

8. The pacemaker of claim 7, wherein said microprocessor chip further comprises:

means for storing said pacing rate signal over a prescribed period of time regardless of whether said pacing rate signal is received by said pacemaker chip.

9. The pacemaker of claim 8 further comprising:

means for producing histogram reports indicative of the pacing rate signals stored by said microprocessor means during said prescribed time period.

10. A rate-responsive pacemaker comprising:

a pulse generator having means for generating pulses at a prescribed rate;

state logic means for controlling said pulse generator, including whether a pulse is to be generated and, if so, at what rate, said state logic means comprising;

state logic registers which, in combination, assume one of a possible plurality of states as a function of signals applied thereto;

memory circuitry addressed by said state logic registers, said memory circuitry having prescribed control signals stored therein at each location which is addressable by said state logic;

timing circuitry which generates timing signals;

sensing circuitry which generates event signals at the occurrence of prescribed events; and

logic circuitry responsive to said control signals, timing signals and event signals having output signals which steer said state logic registers as a function of said control, timing and event signals, said state logic registers continuously cycling through various states as a function of the control, timing and event signals applied to said logic circuitry, a pacing cycle comprising a cycle of said state logic from a prescribed reference state, to at least one other state, and back to said reference state;

a physiological sensor which generates a raw sensor signal having an average amplitude that varies as a function of a physiological environment to which said physiological sensor is subjected;

a conversion circuit coupled to said sensor, said conversion circuit including means for monitoring the average amplitude of said raw sensor signal and means for generating a discrete sensor level index signal as a function of said average amplitude at least once each pacing cycle, said sensor level index signal thereby assuming one of a plurality of possible sensor level signal values once each pacing cycle;

processor means coupled to said conversion circuit for defining a sensor-indicated rate signal as a function of the sensor level index signal for each pacing cycle; and

interface means positioned between said processor means and the memory circuitry of said state logic means for selectively injecting said sensor-indicated rate signal into the control signals of said memory circuitry that is presented to said logic circuitry, whereby said sensor-indicated rate signal, when so injected, cooperates with the event and timing signals already present to influence the rate at which pulses are generated by said pulse generator.

11. The rate-responsive pacemaker of claim 10, wherein said means for measuring the average amplitude of said raw sensor signal comprises:

a rectifying and filter circuit which produces an analog signal having a level which varies as a function of the average amplitude of said raw sensor signal; and

an analog-to-digital conversion circuit which converts said analog signal to a digital signal at least once each pacing cycle, said digital signal comprising said sensor level index signal for that particular pacing cycle.

12. The rate-responsive pacemaker of claim 11, wherein said conversion circuit comprises:

means for converting said raw sensor signal to one of n possible discrete sensor level index signals, n being an integer greater than ten, a first of said sensor level index signals corresponding to said analog signal having a magnitude which is less than 1/nth of a maximum possible magnitude of said analog signal, a second of said sensor level index signals corresponding to an analog signal having a magnitude which is less than 2/nths of the maximum possible magnitude of said analog signal but greater than 1/nth of the maximum magnitude of said analog signal, a third of said sensor level index signals corresponding to an analog signal having a magnitude which is less than 3/nths of the maximum possible magnitude of said analog signal but greater than 2/nths of the maximum possible magnitude of said analog signal, and so on, up to an nth of said sensor level index signals corresponding to an analog signal having a magnitude which is greater than (n-1)/nths of the maximum possible magnitude of said analog signal.

13. The rate-responsive pacemaker of claim 10, wherein said conversion circuit comprises:

means for converting said raw sensor signal to one of n possible discrete sensor level index signals, n being an integer greater than ten, a first of said sensor level index signals corresponding to a raw sensor signal having an average amplitude which falls within a first defined average amplitude zone of said raw sensor signal, a second of said sensor level index signals corresponding to a raw sensor signal having an average amplitude which falls within a second defined average amplitude zone of said raw sensor signal, a third of said sensor level index signals corresponding to a raw sensor signal having an average amplitude which falls within a third defined average amplitude zone of said raw sensor signal, and so on, up to an nth of said sensor level index signals corresponding to a raw sensor signal having an average amplitude which falls within an nth defined average amplitude zone of said raw sensor signal.

14. The rate-responsive pacemaker of claim 13, wherein said n defined average amplitude zones of said raw sensor signal are zones of equal average amplitude.

15. The rate responsive pacemaker of claim 13, wherein the sensor-indicated rate signal defined by said processor means is a predefined minimum value when said sensor level index signal is less than a prescribed rate response threshold, and wherein the sensor-indicated rate signal assumes one of a possible plurality of predefined values greater than said minimum value as a function of said sensor level index signal when said sensor level index signal is greater than or equal to said prescribed rate response threshold.

16. The rate-responsive pacemaker of claim 15 further including programming means for programmably setting the prescribed rate response threshold.

17. The rate-responsive pacemaker of claim 15, wherein said processor means comprises:

means for monitoring and processing the sensor level index signal for a prescribed number of prior cardiac cycles and means for automatically generating said prescribed rate response threshold as a function of said monitoring and processing.

18. The rate-responsive pacemaker of claim 15, wherein said processor means comprises:

means for monitoring and processing the sensor level index signal for a prescribed period of time and means for automatically generating said prescribed rate response threshold as a function of said monitoring and processing.

19. The rate-responsive pacemaker of claim 18, wherein said means for monitoring and processing comprises:

means for averaging the sensor level index signal during said prescribed period of time, and wherein said means for automatically generating said prescribed rate response threshold comprises means for defining said prescribed rate response threshold to be the average sensor level index signal computed over the prescribed period of time plus an offset index signal.

20. The rate-responsive pacemaker of claim 19, wherein the number n of said sensor level index signals comprises thirty-two, each of said sensor level index signals having a value representative of the integers 0 through 31, and further wherein said offset index signal comprises two, whereby if the average sensor level index signal for the prescribed period of time is computed to be, for example, five, the prescribed rate response threshold is automatically set at a value two more than five, or seven.

21. The rate-responsive pacemaker of claim 20, wherein the prescribed period of time over which the sensor level index signal is averaged comprises eighteen hours.

22. A rate-responsive pacing system comprising:

implantable pulse generator means generating a pacing pulse at a rate set by a rate control signal;

means for generating a base rate signal;

implantable sensor means for generating a raw sensor signal indicative of a need to change the rate at which said pacing pulses generated by said pulse generator means;

implantable processor means coupled to said pulse generator means and said sensor means for generating a sensor-indicated rate signal, said processor means for converting said raw sensor signal into one of a plurality of sensor level index signals at prescribed sample times, said conversion causing one of said plurality of sensor level index signals to be generated as a function of the magnitude of said raw sensor signal at each of the sample times, and further wherein said processor means includes means for defining said sensor-indicated rate signal to assume a value which varies as a function of the average amplitude of the sensor level index signals for a plurality of the sample times;

selection means for programmably selecting one of said base rate signal or said sensor-indicated rate signal as the rate control signal controlling said pulse generator means; and

automatic reversion means coupled to said selection means for automatically causing said selection means to select one of said base rate signal or said sensor-indicated rate signal as the rate control signal in the event the other of said base rate signal or said sensor-indicated rate signal is not generated.

23. The rate-responsive pacing system of claim 22, wherein the sensor-indicated rate signal defined by said processor means is a predefined minimum value when said sensor level index signal is less than a prescribed rate response threshold, and wherein the sensor-indicated rate signal assumes one of a possible plurality of predefined values greater than said minimum value as a function of said sensor level index signal when said sensor level index signal is greater than or equal to said prescribed rate response threshold.

24. The rate-responsive pacemaker of claim 23 further including programming means for programmably setting the prescribed rate response threshold.

25. The rate-responsive pacemaker of claim 23, wherein said processor means comprises:

means for monitoring and processing the sensor level index signal for a prescribed period of time, and means for automatically generating said prescribed rate response threshold as a function of said monitoring and processing.

26. The rate-responsive pacemaker of claim 25, wherein said means for monitoring and processing comprises:

means for averaging the sensor level index signal during said prescribed period of time, and wherein said means for automatically generating said prescribed rate response threshold comprises means for defining said prescribed rate response threshold to be the average sensor level index signal computed over the prescribed period of time plus an offset index signal.

27. The rate-responsive pacemaker of claim 22, wherein said processor means further comprises:

histogram means for selectively storing said sensor-indicated rate signals over a selectable period of time, and for providing said stored signals as histogram data upon request.