Flicker-free liquid crystal display driver system

• US 5,041,823 A
• Filed: 12/29/1988
• Issued: 08/20/1991
• Est. Priority Date: 12/29/1988
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Johnson, Michael J., Robinder, Ronald C.
• Primary Examiner(s): Brier, Jeffery A.
• Application Number:
  US07/291,726
• Time in Patent Office: 964 Days
• Field of Search: 340/765, 340/784, 340/793, 340/805, 340/811, 358/230, 358/236, 350/333
• US Class Current: 345/94
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general

Abstract

A flicker-free liquid crystal display driver system driving two groups of pixels with alternating polarities. The spatial differentiation of the two groups, which may be accomplished in terms of even and odd rows or columns, is small so as to diminish detection by a human eye of the flicker in the display. The driver system incorporates a level shifter, switches, drivers, a driver switch control, a holding means and a storage means. Input signals to the system include that of intensity data, a clock and frames. The configuration of the driver system may be of a single-edge or redundant drive. The system may be digital or analog.

Claims

1. A flicker-free liquid crystal display (LCD) system comprising:

a first plurality of lines of LCD pixels;

a second plurality of lines of LCD pixels, wherein said first and second pluralities of lines are interlaced in an alternating fashion to compose a display, such that each line of said first plurality of lines, is adjacent to at least one line of said second plurality of lines;

a first set of drivers connected to said first plurality of lines;

a second set of drivers connected to said second plurality of lines;

switching means, connected to said first and second sets of drivers, for providing a first voltage to said first set of drivers and a second voltage to said second set of drivers, wherein the first and second voltages have opposite polarities, with respect to each other, and the polarities are interchanged by said switching means at each frame change of display data;

interface means, connected to said first and second sets of drivers, for controlling said first and second sets of drivers;

a latching device connected to said interface means;

a shift register connected to said latching device; and

wherein;

the display data and timing signals enter said shift register;

said shift register passes on a portion of display data to said latching device for retention for a certain period of time; and

said interface means receives display data from said shift register via said latching device and provides signals to said first and second sets of drivers.

2. Display of claim 1 wherein the display data are in the form of pulses of various widths which ultimately excite respective pixels to various levels of shades relative to the widths of the pulses.

3. Display of claim 1 wherein said first and second sets of drivers are within said display and any inputs to said drivers enter only a single edge of said display.

4. Display of claim 1 wherein:

said first plurality of lines is the odd-numbered lines counted from a first edge of the display; and

said second plurality of lines is the even-numbered lines counted from the first edge of the display.

5. Display of claim 4 wherein the lines are columns.

6. Display of claim 4 wherein the lines are rows.

7. A flicker-free liquid crystal display (LCD) system comprising:

a first plurality of lines of LCD pixels;

a second plurality of lines of LCD pixels, wherein said first and second pluralities of lines are interlaced in an alternating fashion to compose the display, such that each line of said first plurality of lines, is adjacent to at least one line of said second plurality of lines;

a first set of drivers connected to said first plurality of lines;

a second set of drivers connected to said second plurality of lines;

a first ping-pong sample-and-hold capacitor bank connected to said first and second sets of drivers;

a second ping-pong sample-and-hold capacitor bank connected to said first and second sets of drivers;

a shift register, connected to said first and second set of drivers and to said first and second ping-pong sample-and-hold capacitor banks, for receiving clock signals and display data, and for controlling said first and second sets of drivers; and

switching means, connected to said first and second sets of drivers, for providing a first variable voltage to said first set of drivers and a second variable voltage to said second set of drivers, wherein the first and second variable voltages have opposite polarities, with respect to each other, and the polarities are interchanged by said switching means in response to a frame signal, and for receiving the variable first and second voltages wherein the first and second voltages have variations that represent intensity data for the pixels.