Method of forming an IC chip with self-aligned thin film resistors

• US 5,043,295 A
• Filed: 06/20/1989
• Issued: 08/27/1991
• Est. Priority Date: 09/09/1987
• Status: Expired due to Term

• Current Assignee: Cynthia E. Anderson, Paul A. Ruggerio
• Original Assignee: Cynthia E. Anderson, Paul A. Ruggerio
• Inventors: Ruggerio, Paul A., Anderson, Cynthia E.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Nguyen, Tuan
• Application Number:
  US07/368,825
• Time in Patent Office: 798 Days
• Field of Search: 437/47, 437/918, 437/194, 437/60, 437/190, 148/DIG. 136, 357/51, 338/306, 338/308, 156/649, 156/650, 156/651, 156/652
• US Class Current: 438/384
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/136 Resistors

Abstract

Process of making an IC chip with thin film resistors, and IC chips made by such process, wherein a chip substrate first is covered with layers of thin film and interconnect material (with an intermediate barrier layer if needed), such layers being etched away in predetermined regions in accordance with the metal interconnect pattern, the remaining layered material being aligned vertically, and thereafter, in a section of the remaining material, etching away the interconnect material (and barrier material if used) to expose the thin film material to form a thin film resistor which is self-aligned withe the adjoining sections of interconnect conductors. The material in the predetermined regions may be etched by a dry-etch (plasma) or by a wet-etch.

Claims

1. A process of forming an IC chip with at least one thin film resistor comprising:

depositing a layer of thin film material on a predetermined area of a substrate;

depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material throughout said predetermined area thereof;

removing both said thin film and interconnect layers in predetermined regions of said area while leaving at least a part of the remaining layers aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip;

said remaining part of said layers including at least one segment with thin film material to be developed as a resistor;

and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material as a resistor between adjoining sections of said segment.

2. The process of claim 1, wherein said thin film and interconnect layers are removed in said predetermined regions by applications of a dry etch.

3. The process of claim 2, including the step of depositing a layer of barrier material between said thin film material and said interconnect material, said barrier material being removed in said predetermined regions simultaneously with said thin film and interconnect layers.

4. The process of claim 3, wherein said thin film material is Silicon Chrome.

5. The process of claim 3, wherein said barrier material is TiW.

6. The process of claim 2, wherein said dry etch comprises a chlorinated gas in a plasma.

7. The process of claim 1, wherein said interconnect layer is removed in said predetermined regions by application of a wet etch.

8. The process of claim 7, including the step of depositing a layer of barrier material between said thin film layer and said interconnect material, said barrier material being removed from said predetermined regions by application of a wet etch.

9. The process of claim 8, wherein the wet etch applications comprise PAN etch followed by H₂ O₂.

10. The process of claim 9, wherein said thin film material is removed from said predetermined regions by application of a plasma etch.

11. A process of forming an IC chip with at least one thin film resistor comprising:

depositing a layer of thin film material on a predetermined area of a substrate;

depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material therebeneath;

removing both said thin film and interconnect layers in predetermined regions of said predetermined area, the removal being carried out by a process which provides that the side edges of the remaining layers are aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip;

said remaining layers including at least one segment wherein at least part of the thin film material is to be developed as a resistor forming part of the circuit of said IC chip; and

removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material without any interconnect directly thereabove, thereby to provide said resistor between spaced-apart sections of said one segment.

12. The process of claim 11, wherein said thin film and interconnect layers are removed in said predetermined regions by application of a dry etch.

13. The process of claim 12, including the step of depositing a layer of barrier material between said thin film material and said interconnect material, said barrier material being removed in said predetermined regions simultaneously with said removal of said thin film and interconnect layers.

14. The process of claim 11, wherein said interconnect layer is removed from said predetermined regions by application of a wet etch.

15. The process of claim 14, wherein said thin film material is removed from said predetermined regions by application of a plasma etch.