Adaptable CMOS winner-take all circuit
First Claim
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1. An adaptable circuit, communicating with a plurality of current-carrying lines, for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing, including:
- a plurality of MOS current mirrors, each of said current mirrors including an input node, an output node, a driving MOS current mirror transistor and a driven MOS current mirror transistor, the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a source of fixed positive voltage, the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to one electrode of a first MOS capacitor, the gate of said driven MOS current mirror transistor connected to a floating node, the second electrode of said first MOS capacitor comprising a portion of said floating node, drain of said driven MOS current mirror transistor comprising said output node and connected to the gate of said follower transistor,a second MOS capacitor associated with each of said plurality of current mirrors, each said second MOS capacitor having as a first electrode a portion of the floating node in the current mirror with which it is associated, and as a second electrode a second node,a pulldown transistor associated with each of said current mirrors, each of said pulldown transistors having its source connected to a source of fixed negative voltage, and its gate connected to a common pulldown gate line,a pulldown gate bias transistor, having its source connected to said source of negative voltage, its gate connected to a source of bias voltage,a follower transistor associated with each of said current mirrors, having its gate connected to the output of the current mirror with which it is associated, and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line,means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line, and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit, and for connecting said common pulldown gate line to a source of fixed voltage, for connecting each of said second nodes to the output node of said current mirror with which it is associated, and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit,an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltages of said circuit can be adapted while a source of ultraviolet light is present during said adapting mode of said circuit.
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Abstract
An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.
131 Citations
1 Claim
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1. An adaptable circuit, communicating with a plurality of current-carrying lines, for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing, including:
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a plurality of MOS current mirrors, each of said current mirrors including an input node, an output node, a driving MOS current mirror transistor and a driven MOS current mirror transistor, the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a source of fixed positive voltage, the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to one electrode of a first MOS capacitor, the gate of said driven MOS current mirror transistor connected to a floating node, the second electrode of said first MOS capacitor comprising a portion of said floating node, drain of said driven MOS current mirror transistor comprising said output node and connected to the gate of said follower transistor, a second MOS capacitor associated with each of said plurality of current mirrors, each said second MOS capacitor having as a first electrode a portion of the floating node in the current mirror with which it is associated, and as a second electrode a second node, a pulldown transistor associated with each of said current mirrors, each of said pulldown transistors having its source connected to a source of fixed negative voltage, and its gate connected to a common pulldown gate line, a pulldown gate bias transistor, having its source connected to said source of negative voltage, its gate connected to a source of bias voltage, a follower transistor associated with each of said current mirrors, having its gate connected to the output of the current mirror with which it is associated, and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line, means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line, and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit, and for connecting said common pulldown gate line to a source of fixed voltage, for connecting each of said second nodes to the output node of said current mirror with which it is associated, and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltages of said circuit can be adapted while a source of ultraviolet light is present during said adapting mode of said circuit.
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Specification
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Current AssigneeSynaptics Incorporated
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Original AssigneeSynaptics Incorporated
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InventorsAllen, Timothy P., Mead, Carver A.
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Primary Examiner(s)Miller, Stanley D.
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Assistant Examiner(s)TRAN, TOAN V
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Application NumberUS07/608,972Time in Patent Office321 DaysField of Search307/246, 307/311, 307/264, 307/482, 307/578, 307/278, 307/350, 307/351, 323/316, 323/317, 330/288, 357/23.5, 365/185US Class Current365/185.21CPC Class CodesG06N 3/063 using electronic meansH01L 27/0629 in combination with diodes,...H03F 1/0261 with control of the polaris...H03F 1/303 using a switching device H0...H03F 3/45479 characterised by the way of...H03F 3/45753 using switching means, e.g....H03F 3/45977 using switching means, e.g....
