Filter system having an adaptive control for updating filter samples

• US 5,053,983 A
• Filed: 04/04/1986
• Issued: 10/01/1991
• Est. Priority Date: 04/19/1971
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/849,071
• Time in Patent Office: 2,006 Days
• Field of Search: 364/724, 364/825, 364/724.03, 364/724.04, 364/724.18, 364/825
• US Class Current: 708/306
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/0121 Operation of devices; Circuit arrangements, not otherwise provided for in this subclass
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03H 17/0291 : Digital and sampled data filters

Abstract

An adaptive filter system is provided to improve filtering operations. Adaptive logic monitors filtered information to determine when sufficient filtering has been performed to perform outputting, further processing, or other operations. In addition, saturation logic monitors filtered information to detect overflow conditions for compensation thereof. In one configuration, filtering operations are performed iteratively, building up the signal to noise ratio of the signals; where filtered signals are monitored to determine when the filtered signals have reached or exceeded a threshold magnitude, as indicative of sufficient signal to noise ratio enhancement, and to prevent the filtered signals from overflowing.

Claims

1. A filtering system comprising:

an input signal source for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered output signal samples;

a sampled filter processor for updating the filtered output signal samples stored in said output memory, said sampled filter processor including

1) a multiplier for generating product signal samples by multiplying the input signal samples generated by said input signal source and the reference signal samples generated by said reference signal circuit and

2) an adder for updating the filtered output signal samples stored in said output memory by adding the product signal samples generated by said multiplier to the filtered output signal samples stored in said output memory;

a detector for generating a filter complete signal in response to detection of a selected magnitude of the filtered output signal samples;

a disable circuit for disabling updating of the filtered output signal samples stored in said output memory in response to the detection of the selected magnitude of the filtered output signal samples stored in said output memory; and

an output circuit for generating an output control signal to an external device indicative of the occurrence of the filter complete signal generated by said detector.

2. The system as set forth in claim 1 above, wherein said reference signal circuit includes a Fourier transform reference signal circuit for generating the reference signal samples as Fourier transform reference signal samples;

wherein said output memory includes a Fourier transform output memory for storing the filtered output signal samples as Fourier transform filtered output signal samples;

wherein said sampled filter processor includes a Fourier transform filter processor for updating the Fourier transform filtered output signal samples stored in said Fourier transform output memory.

3. The system as set forth in claim 1 above, wherein said input signal source includes a charge coupled device for shifting analog signal samples and an analog to digital converter for generating the input signal samples as digital whole number input signal samples in response to the analog signal samples shifted by said charge coupled device;

wherein said reference signal circuit includes an FFT reference read only memory for storing the reference signal samples as digital whole number stored FFT reference signal samples in read only memory form;

wherein said output memory includes an integrated circuit random access output memory for storing the filtered output signal samples as whole number FFT filtered output signal samples;

wherein said sampled filter processor includes an FFT sampled filter processor for updating the FFT filtered output signal samples stored in said output memory;

wherein said detector includes means for detecting filtered output signal samples that are not below a selected magnitude and a counter for generating the filter complete signal in response to detection of a programmable quantity of the selected magnitude whole number FFT filtered output signal samples that are not below the selected magnitude having values that are not less than the value of the selected magnitude by counting the detected whole number FFT filtered output signal samples that are not below the selected magnitude;

wherein said disable circuit includes a NAND gate for disabling the updating of the filtered output signal samples stored in said output memory in response to the detection of the programmed quantity of the filtered output signal samples stored in said output memory;

wherein said external device includes a supervisory computer for processing the filtered output signal samples stored in said output memory in response to the output control signal generated by said output circuit; and

wherein said system further comprises an output memory initialization circuit for initializing the filtered output signal samples to zero by clearing said output memory.

17. The system as set forth in claim 1 above, wherein said input signal source includes means for generating the input signal samples as single bit input signal samples;

wherein said reference signal circuit includes means for generating the reference signal samples as single bit reference signal samples;

wherein said output memory includes means for storing the filtered output signal samples as multi-bit digital filtered output signal samples;

wherein said detector includes a digital gate for generating the update control signal in response to detection of a first selected magnitude of the multi-bit digital filtered output signal samples stored in said output memory;

wherein said system further comprises

a counter for generating an update control signal related digital count number by counting the update control signal generated by said detector and

a saturation detector for generating a saturation control signal in response to detection of a second predetermined saturation magnitude of the multi-bit digital filtered output signal samples stored in said output memory;

wherein said filter includes means for updating the multi-bit digital filtered output signal samples stored in said output memory under control of the update control signal related digital count number generated by said counter and under control of the saturation control signal generated by said saturation detector; and

wherein said multiplier includes means for generating single bit product signal samples by multiplying each of the single bit input signal samples by a single bit reference signal sample and wherein said adder includes means for updating the multi-bit filtered output signal samples stored in said output memory by adding each of the single bit product signal samples to the multi-bit output signal samples stored in said output memory.

4. A filtering system comprising:

an input signal source for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered output signal samples;

a sampled filter processor for updating the filtered output signal samples stored in said output memory, said sampled filter processor including

1) a multiplier for generating product signal samples by multiplying the input signal samples generated by said input signal source and the reference signal samples generated by said reference signal circuit and

2) an adder for updating the filtered output signal samples stored in said output memory by adding the product signal samples generated by said multiplier to the filtered output signal samples stored in said output memory;

a saturation circuit for saturating the filtered output signal samples stored in said output memory to prevent overflow caused by updating of the filtered output signal samples by said filter processor;

a detector for generating a filter complete signal in response to detection of a selected magnitude of the filtered output signal samples;

a disable circuit for disabling updating of the filtered output signal samples stored in said output memory in response to the detection of the selected magnitude of the filtered output signal samples stored in said output memory; and

an output circuit for generating an output control signal to an external device indicative of the occurrence of the filter complete signal generated by said detector.

5. A sampled filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered signal samples;

a detector for generating a control signal in response to detection of a predetermined magnitude of a filtered signal sample stored in said output memory;

a counter for generating a count number signal by counting the control signals generated by said detector; and

a sampled filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated by said input circuit under control of the count number signal generated by said counter, said sampled filter processor including control logic for enabling of the updating of the filtered signal samples stored in said output memory when the count number signal is less than a predetermined count magnitude and for disabling of the updating of the filtered signal samples stored in said output memory when the count number signal is equal to the predetermined count magnitude.

6. The system as set forth in claim 5 above, wherein said output memory includes a correlator output memory for storing the filtered signal samples as correlated filtered signal samples;

wherein said sampled filter processor includes a correlator for updating the correlated filtered signal samples stored in said correlator output memory in response to the input signal samples generated by said input circuit under control of the count number signal generated by said counter.

7. A sampled filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered signal samples;

a detector for generating a control signal in response to detection of a predetermined magnitude of a filtered signal sample stored in said output memory;

a counter for generating a count number signal by counting the control signals generated by said detector;

a control circuit for generating a saturated magnitude control signal in response to detection of a saturated magnitude of at least one filtered output signal sample stored in said output memory; and

a sampled filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated by said input circuit under control of the saturated magnitude control signal to saturate updating of the at least one filtered signal sample having a saturated magnitude that is detected by said control circuit and under control of the count number signal generated by said counter, said sampled filter processor including control logic for enabling of the updating of the filtered signal samples stored in said output memory when the count number signal is less than a predetermined count magnitude and for disabling of the updating of the filtered signal samples stored in said output memory when the count number signal is equal to the predetermined magnitude.

8. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered signal samples;

a detector for generating a control signal in response to detection of a predetermined magnitude of a filtered signal sample stored in said output memory;

a counter for generating a count number signal by counting the control signals generated by said detector;

a sampled filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated by said input circuit under control of the count number signal generated by said counter, said sampled filter processor including control logic for enabling of the updating of the filtered signal samples stored in said output memory when the count number signal is less than a predetermined count magnitude and for disabling of the updating of the filtered signal samples stored in said output memory when the count number signal is equal to the predetermined magnitude; and

a saturation circuit for saturating the filtered signal samples stored in said output memory to prevent overflow caused by updating of the filtered signal samples by said sampled filter processor.

9. A sampled filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a detector for generating a control signal in response to detection of a selected magnitude of a filtered signal sample stored in said output memory; and

a filter for updating the filtered signal samples stored in said output memory under control of the control signal generated by said detector, wherein said filter includes

1) a multiplier for generating product signal samples by multiplying the input signal samples stored in said output memory and the reference signal samples generated by said reference signal circuit and

2) an adder for adding the product signal samples generated by said multiplier to the filtered signal samples stored in said output memory under control of the control signal generated with said detector.

10. A sampled filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a detector for generating a control signal in response to detection of a selected magnitude of a filtered signal sample stored in said output memory;

a control circuit for generating a saturated magnitude control signal in response to detection of a saturated magnitude of at least one of the filtered signal samples stored in said output memory; and

a filter for updating the filtered signal samples stored in said output memory under control of the control signal generated by said detector, wherein said filter includes

1) a multiplier for generating product signal samples by multiplying the input signal samples stored in said output memory and the reference signal samples generated by said reference signal circuit,

2) an adder for adding the product signal samples generated by said multiplier to the filtered signal samples stored in said output memory under control of the control signal generated with said detector, and

3) a saturation circuit for performing the updating of the filtered signal samples stored in said output memory under control of the saturated magnitude control signal to saturate updating of the at least one filtered signal sample having a saturated magnitude that is detected by said control circuit.

11. A sampled filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a detector for generating control signals in response to detection of a magnitude of the filtered signal samples stored in said output memory;

a counter for generating a count number signal by counting the control signals generated by said detector; and

a filter for enabling updating of the filtered signal samples stored in said output memory when the count number signal is indicative of a count that is less than a predetermined magnitude and for disabling updating of the filtered signal samples stored in said output memory when the count number signal is indicative of a count that is greater than a predetermined magnitude, wherein said filter includes

1) a multiplier for generating product signal samples by multiplying each of the input signal samples by a reference signal sample and

2) an adder for adding each of the product signal samples to at least one of the filtered signal samples stored in said output memory under control of the control signals generated by said detector.

12. A sampled filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a detector for generating control signals in response to detection of a magnitude of the filtered signal samples stored in said output memory;

a counter for generating a count number signal by counting the control signals generated by said detector;

a filter for enabling updating of the filtered signal samples stored in said output memory when the count number signal is indicative of a count that is less than a predetermined magnitude and for disabling updating of the filtered signal samples stored in said output memory when the count number signal is indicative of a count that is greater than a predetermined magnitude, wherein said filter includes

1) a multiplier for generating product signal samples by multiplying each of the input signal samples by a reference signal sample and

2) an adder for adding each of the product signal samples to at least one of the filtered signal samples stored in said output memory under control of the control signals generated by said detector; and

a saturation circuit for saturating the filtered signal samples stored in said output memory to prevent overflow caused by updating of the filtered signal samples by said filter.

13. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered signal samples;

a detector for generating a saturation limit control signal by monitoring the filtered signal samples to detect a saturation limit magnitude of a filtered signal sample stored in said output memory; and

a sampled filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated by said input circuit under control of the saturation limit control signal generated by said detector to prevent overflow of the filtered signal samples.

14. The system as set forth in claim 13 above, further comprising:

a signal to noise ratio detector for detecting signal to noise ratio of the filtered signal samples stored in said output memory and

a signal to noise ratio controller for controlling said sampled filter processor to update the filtered signal samples stored in said output memory when the signal to noise ratio of the filtered signal samples stored in said output memory is below a selected magnitude and to discontinue updating of the filtered signal samples stored in said output memory when the signal to noise ratio of the filtered signal samples stored in said output memory is at a selected magnitude.

15. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered signal samples;

a detector for generating a saturation limit control signal by monitoring the filtered signal samples to detect a saturation limit magnitude of a filtered signal sample stored in said output memory;

a reference circuit for generating correlation reference signal samples; and

a correlation filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated by said input circuit under control of the saturation limit control signal generated by said detector to prevent overflow of the filtered signal samples;

wherein said correlation filter processor includes

1) a multiplier for generating product signal samples by multiplying the input signal samples and the correlation reference signal samples and

2) an adder for updating the filtered signal samples stored in said output memory by adding the product signal samples generated by said multiplier to the filtered output signal samples stored in said output memory.

16. A filtering system comprising:

an input signal source for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered output signal samples;

a detector for generating an update control signal in response to detection of a selected magnitude of the filtered output signal samples stored in said output memory; and

a filter for updating the filtered output signal samples stored in said output memory under control of the update control signal generated by said detector, said filter including

1) a multiplier for generating product signal samples by multiplying the input signal samples generated by said input signal source and the reference signal samples generated by said reference signal circuit and

2) an adder for updating the filtered output signal samples stored in said output memory by adding the product signal samples generated by said multiplier to the filtered output signal samples stored in said output memory.

18. A sample filter system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered signal samples;

a filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated by said input circuit;

a detector for monitoring magnitude of the filtered signal samples stored in said output memory to generate a filtering complete control signal that is indicative of a magnitude of at least one of the filtered signal samples building up to a selected magnitude; and

an output circuit for generating an external control signal for controlling an external device in response to the filtering complete control signal.

19. A correlation filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating correlation reference signal samples;

a correlation output memory for storing correlation filtered signal samples;

a detector for generating a detector control signal in response to detection of a magnitude of the correlation filtered signal samples stored in said correlation output memory; and

a correlation filter for updating of the correlation filtered signal samples stored in said correlation output memory under control of the control signal generated by said detector, said correlation filter including

1) a multiplier for generating product signal samples by multiplying the input signal samples generated by said input circuit and the correlation reference signal samples generated by said reference signal circuit and

2) an adder for updating the correlation filtered signal samples stored in said correlation output memory by adding the product signal samples generated by said multiplier to the correlation filtered signal samples stored in said correlation output memory.

20. A sampled filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a sampled filter for updating the filtered signal samples stored in said output memory, wherein said sampled filter includes

1) a multiplier for generating product signal samples by multiplying each of the input signal samples by a reference signal sample and

2) an adder for adding each of the product signal samples to at least one of the filtered signal samples stored in said output memory;

a detector for monitoring magnitude of the filtered signal samples stored in said output memory to generate a control signal in response to detection of a selected magnitude of a filtered signal sample stored in said output memory; and

a supervisory computer for generating a computer operation in response to the control signal generated by said detector.

21. A sampled filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a sampled filter for updating the filtered signal samples stored in said output memory, wherein said sampled filter includes

1) a multiplier for generating product signal samples by multiplying each of the input signal samples by a reference signal sample and

2) an adder for adding each of the product signal samples to at least one of the filtered signal samples stored in said output memory;

a saturation circuit for saturating the filtered signal samples stored in said output memory to prevent overflow caused by updating of the filtered signal samples by said sampled filter;

a detector for monitoring magnitude of the filtered signal samples stored in said output memory to generate a control signal in response to detection of a selected magnitude of a filtered signal sample stored in said output memory; and

a supervisory computer for generating a computer operation in reponse to the control signal generated by said detector.

22. A filtering system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a signal to noise ratio detector for generating a signal to noise ratio control signal in response to a selected signal to noise ratio of the filtered signal samples stored in said output memory; and

a filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated with said input circuit and in response to the reference signal samples generated with said reference signal circuit under control of the signal to noise ratio control signal generated by said signal to noise ratio detector.

23. A filtering system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a signal to noise ratio detector for generating a signal to noise ratio control signal in response to a selected signal to noise ratio of the filterd signal samples stored in said output memory;

a filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated with said input circuit under control of the signal to noise ratio control signal generated by said signal to noise ratio detector; and

a saturation circuit for saturating the filtered signal samples stored in said output memory to prevent overflow caused by updating of the filtered signal samples by said filter processor.

24. A filter system comprising:

an input circuit for generating input signal samples;

a reference circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated by said input circuit, said filter processor including

1) a multiplier for generating product signal samples by multiplying the input signal samples generated by said input circuit and the reference signal samples generated by said reference circuit and

2) an adder for adding the product signal samples generated by said multiplier to the filtered signal samples stored in said output memory;

a detector for monitoring the filtered signal samples stored in said output memory to detect a selected magnitude of at least one of the filtered signal samples; and

a controller for controlling said filter processor to discontinue said updating of the filtered signal samples stored in said output memory when the selected magnitude of the at least one of the filtered signal samples stored in said output memory is detected by said detector.

25. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

a control circuit for generating a saturated magnitude control signal in response to detection of a saturated magnitude of at least one filtered output signal sample stored in said output memory; and

a filter processor for updating the filtered output signal samples stored in said output memory in response to the input signal samples under control of the saturated magnitude control signal to saturate updating of the at least one filtered output signal sample having a saturated magnitude that is detected by said control circuit.

26. The system as set forth in claim 25 above, further comprising:

a signal to noise ratio detector for detecting signal to noise ratio of the filtered output signal samples stored in said output memory and

a signal to noise ratio controller for controlling said filter processor to update the filtered output signal samples stored in said output memory when the signal to noise ratio of the filtered output signal samples stored in said output memory is below a selected magnitude and to discontinue updating of the filtered output signal samples stored in said output memory when the signal to noise ratio of the filtered output signal samples stored in said output memory is at a selected magnitude.

27. A filtering system comprising:

an input circuit for generating input signal samples;

a Fourier transform output memory for storing Fourier transform filtered output signal samples;

a control circuit for generating a saturated magnitude control signal in response to detection of a saturated magnitude of at least one filtered output signal sample stored in said output memory; and

a Fourier transform filter processor for updating the Fourier transform filtered output signal samples stored in said Fourier transform output memory in response to the input signal samples under control of the saturated magnitude control signal to saturate updating of the at least one output Fourier transform signal sample having a saturated magnitude that is detected by said control circuit.

28. A filter system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered signal samples;

a filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated with said input circuit under control of a control circuit;

a programming circuit for generating a programmable number;

a programmable counter being programmable with said programmable number generated with said programming circuit for generating a control signal in response to detection of a programmable number of updates by said filter processor being completed; and

a control circuit for terminating the updating of the filtered signal samples stored in said output memory by said filter processor in response to the control signal generated by said programmable counter indicating that the programmable number of updates by said filter processor have been completed.

29. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

a control circuit for generating a saturated magnitude control signal in response to detection of a saturated magnitude of at least one filtered output signal sample stored in said output memory;

a filter processor for updating the filtered output signal samples stored in said output memory in response to the input signal samples under control of the saturated magnitude control signal to saturate updating of the at least one filtered output signal sample having a saturated magnitude that is detected by said control circuit; and

a signal to noise ratio detection circuit for generating a signal to noise ratio control signal by monitoring the filtered output signal samples to detect a predetermined signal to noise ratio magnitude.

30. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

a sampled filter processor for updating the filtered output signal samples stored in said output memory in response to filter processing of the input signal samples generated by said input circuit; and

a signal to noise ratio detection circuit for generating a signal to noise ratio control signal by monitoring the filtered output signal samples to detect a predetermined signal to noise ratio magnitude.

31. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

a sampled filter processor for updating the filtered output signal samples stored in said output memory in response to filter processing of the input signal samples generated by said input circuit; and

a detection circuit for generating a filtering completed control signal by monitoring the filtered output signal samples to detect a predetermined quantity of filtered output signal samples having a selected magnitude.

32. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

a saturation detector circuit for generating a detector signal by monitoring the output signal samples stored in said output memory, said saturation detector circuit generating a first condition of the detector signal in response to an output signal sample having a magnitude that is below a predetermined saturation magnitude and said saturation detector circuit generating a second condition of the detector signal in response to an output signal sample having a magnitude that is not below the predetermined saturation magnitude;

a filter processor for filtering the input signal samples, wherein said filter processor includes an updating circuit for updating the filtered output signal samples that have a magnitude that is below a predetermined saturation magnitude in response to the input signal samples under control of the first condition of the detector and wherein said filter processor includes a saturation circuit for saturating the filtered output signal samples that have a magnitude that is not below the predetermined saturation magnitude under control of the second condition of the detector signal;

a signal to noise ratio detector for detecting signal to noise ratio of the filtered output signal samples stored in said output memory; and

a signal to noise ratio controller for controlling said filter processor to update the filtered output signal samples stored in said output memory when the signal to noise ratio of the filtered output signal samples stored in said output memory is below a selected magnitude and to discontinue updating of the filtered output signal samples stored in said output memory when the signal to noise ratio of the filtered output signal samples stored in said output memory is at a selected magnitude.

33. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

a filter processor for updating the filtered output signal samples stored by said output memory in response to the input signal samples;

a detector circuit for generating a detector signal by monitoring the output signal samples stored in said output memory, said detector circuit generating a first condition of the detector signal in response to an output signal sample having a magnitude that is below a predetermined magnitude and said detector circuit generating a second condition of the detector signal in response to an output signal sample having a magnitude that is not below the predetermined magnitude;

a counter for counting the second conditions of the detector signal generated by said detector circuit to generate a count number indicative of the number of output signal samples having a magnitude that is not below the predetermined magnitude; and

a control circuit for enabling updating of the filtered output signal samples by said filter processor in response to a count number generated by said counter that is less than a predetermined number magnitude and for disabling updating of the filtered output signal samples by said filter processor in response to a count number generated by said counter that is equal to a predetermined number magnitude.

34. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

a saturation detector circuit for generating a saturation detector signal by monitoring the output signal samples stored in said output memory, said saturation detector circuit generating a first condition of the saturation detector signal in response to an output signal sample having a magnitude that is below a predetermined saturation magnitude and said saturation detector circuit generating a second condition of the saturation detector signal in response to an output signal sample having a magnitude that is not below the predetermined saturation magnitude;

a filter processor for filtering the input signal samples, wherein said filter processor includes an updating circuit for updating the filtered output signal samples that have a magnitude that is below a predetermined saturation magnitude in response to the input signal samples under control of the first condition of the saturation detector and wherein said filter processor includes a saturation circuit for saturating the filtered output signal samples that have a magnitude that is not below the predetermined saturation magnitude under control of the second condition of the saturation detector signal;

a magnitude detector circuit for generating a magnitude detector signal by monitoring the output signal samples stored in said output memory, said magnitude detector circuit generating a first condition of the magnitude detector signal in response to an output signal sample having a magnitude that is below a predetermined magnitude and said magnitude detector circuit generating a second condition of the magnitude detector signal in response to an output signal sample having a magnitude that is not below the predetermined magnitude;

a counter for counting the second conditions of the magnitude detector signal generated by said second circuit to generate a count number indicative of the number of output signal samples having a magnitude that is not below the predetermined magnitude; and

a control circuit for enabling updating of the filtered output signal samples by said filter processor updating circuit in response to a count number generated by said counter that is less than a predetermined number magnitude and for disabling updating of the filtered output signal samples by said filter processor in response to a count number generated by said counter that is equal to a predetermined number magnitude.

35. A filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a filter processor for updating the filtered signal samples stored in said output memory, said filter processor including

1) a multiplier for generating product signal samples by multiplying the input signal samples generated by said input circuit and the reference signal samples generated by said reference signal circuit and

2) an adder for adding the product signal samples generated by said multiplier and the filtered signal samples stored in said output memory; and

a saturation circuit for saturating the filtered signal samples stored in said output memory to prevent overflow caused by updating of the filtered signal samples by said filter processor.

36. A filter system comprising:

an input circuit for generating input signal samples;

a reference signal circuit for generating reference signal samples;

an output memory for storing filtered signal samples;

a filter processor for updating the filtered signal samples stored in said output memory, said filter processor including

1) a multiplier for generating product signal samples by multiplying the input signal samples generated by said input circuit and the reference signal samples generated by said reference signal circuit and

2) an adder for adding the product signal samples generated by said multiplier and the filtered signal samples stored in said output memory;

a signal to noise ratio detector for detecting signal to noise ratio of the filtered signal samples stored in said output memory; and

a signal to noise ratio controller for controlling said filter processor to update the filtered signal samples stored in said output memory when the signal to noise ratio of the filtered signal samples stored in said output memory is below a selected magnitude and to discontinue updating of the filtered signal samples stored in said output memory when the signal to noise ratio of the filtered signal samples stored in said output memory is at a selected magnitude.

37. A filtering system comprising:

an input circuit for generating input signal samples;

a Fourier transform output memory for storing Fourier transform filtered output signal samples;

an adaptive control circuit for generating an update control signal to adaptively control filtering of the input signal samples; and

an iterative Fourier transform filter for iteratively updating the Fourier transform filtered output signal samples stored in said correlation output memory by Fourier transform filtering the input signal samples under control of the update control signal.

38. A filtering system comprising:

an input circuit for generating input signal samples;

an output memory for storing filtered output signal samples;

an iterative filter for iteratively updating the filtered output signal samples by filtering the input signal samples under control of an update control signal; and

a saturation limit adaptive control circuit for generating the update control signal to adaptively control the filtering of the input signal samples by updating of the filtered output signal samples to limit the magnitude of the filtered output signal samples to a predetermined saturation magnitude.