CMOS amplifier with offset adaptation

• US 5,059,920 A
• Filed: 05/18/1990
• Issued: 10/22/1991
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Allen, Timothy P., Mead, Carver A., Anderson, Janeen D. W., Wall, Michael F.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/525,764
• Time in Patent Office: 522 Days
• Field of Search: 330/9, 330/261, 330/264, 330/296, 330/307, 330/253, 307/491, 307/494
• US Class Current: 330/253
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.

An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.

An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An electrical learning means allows the floating node to be charged or discharged to a voltage which effectively cancels the input offset voltage.

Claims

1. An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit, including:

an input node,

an output node,

an amplifier having an input connected to a floating node and an output connected to said output node,

an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node,

a source of an electrical control signal,

electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal.

2. The auto-compensating amplifier of claim 1 wherein said electrical control signal is a monotonic function of the voltage on said floating node.

3. The auto-compensating amplifier of claim 1 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

4. The auto-compensating amplifier of claim 3 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate,

an n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

means for injecting electrons into said p-type region,

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

5. An analog MOS auto-compensating amplifier fabricated as a part of an integrated circuit, including:

an input node,

an output node,

an amplifier having an input connected to a floating node and an output connected to said output node,

an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node,

a source of an electrical control signal,

electron removal means coupled to said floating node and responsive to said electrical control signal for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron removal means .operating to vary the rate of removal of electrons from said floating node in response to the magnitude of said electrical control signal.

6. The auto-compensating amplifier of claim 5 wherein said electrical control signal is a function-of the voltage on said floating node.

7. The auto-compensating amplifier of claim 5 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

8. The auto-compensating amplifier of claim 7 wherein, said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

9. An analog MOS auto-compensating amplifier fabricated as a part of an integrated circuit on a semiconductor substrate, including:

an input node,

an output node,

an amplifier having an input connected to a floating node and an output connected to said output node,

an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node,

sources of first and second electrical control signals,

electron injecting means coupled to said floating node and responsive to said first electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said first electrical control signal,

electron removal means coupled to said floating node and responsive to said second electrical control signal for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron removal means operating to vary the rate of removal of electrons from said floating node in response to the magnitude of said second electrical control signal.

10. The auto-compensating amplifier of claim 9 therein said first and second electrical control signals are functions of the voltage on said floating node.

11. The auto-compensating amplifier of claim 9 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

12. The auto-compensating amplifier of claim 11 wherein said electron injecting means is a semiconductor structure for performing non-avalanche hot electron injection including:

a p-type region in said semiconductor substrate,

an n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

means for injecting electrons into said p-type region,

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

13. The auto-compensating amplifier of claim 9 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

14. The auto-compensating amplifier of claim 13 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

15. An analog MOS auto-compensating amplifier fabricated as a part of an integrated circuit on a semiconductor substrate, including:

an input node,

an output node,

an amplifier having an input connected to a floating node and an output connected to said output node,

a MOS capacitor connected between said input node and said floating node,

electrical control signal generating means coupled to said floating node, for selectively generating an electrical control signal having a magnitude which is a monotonic function of the voltage on said floating node,

electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron injecting means, when enabled, operating to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node.

16. The auto-compensating amplifier of claim 15 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

17. The auto-compensating amplifier of claim 16 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate,

an n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

means for injecting electrons into said p-type region,

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

18. An analog MOS auto-compensating amplifier fabricated as a part of an integrated circuit, including:

an input node,

an output node,

an amplifier having an input connected to a floating node and an output connected to said output node,

an MOS capacitor connected between said input node and said floating node,

electrical control signal generating means coupled to said floating node, for selectively generating a first electrical control signal having a magnitude which is a first monotonic function of the voltage on said floating node, and a second electrical control signal having a magnitude which is a second monotonic function of the voltage on said floating node,

electron injecting means coupled to said floating node and responsive to said first electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron injecting means operating to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node,

electron removal means coupled to said floating node and responsive to said second electrical control signal for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron removal means operating to increase the rate of removal of electrons from said floating node in response to a decrease in voltage on said floating node.