CCD imager with positive and mirror image output

• US 5,060,072 A
• Filed: 09/17/1990
• Issued: 10/22/1991
• Est. Priority Date: 09/21/1989
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kato, Naoki, Hojo, Junichi, Fujikawa, Kazuhide, Wakayama, Toshiaki
• Primary Examiner(s): Britton, Howard W.
• Assistant Examiner(s): Ho, Tuan V.
• Application Number:
  US07/583,218
• Time in Patent Office: 400 Days
• Field of Search: 358/209, 358/213.11, 358/213.13, 358/213.15, 358/213.19, 358/213.24, 358/213.26, 358/213.29, 358/223, 358/108
• US Class Current: 348/316
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 5/262 Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects

Abstract

A charge-coupled device (CCD) imager is comprised of a CCD image sensor, a horizontal register for delivering an image signal from the CCD image sensor, the horizontal register being formed of an effective bit portion corresponding to the CCD image sensor and first and second dummy bit portions of a predetermined length which are located at both sides of the effective bit portion, and first and second output portions provided in succession to the first and second dummy bit portions to provide a positive image signal and a mirror image signal, wherein the effective bit portion is provided with four bus lines through which a transfer clock is supplied to the horizontal register and the first and second dummy bit portions are provided with two bus lines through which a transfer clock is supplied to the horizontal register. Thus, the CCD imager can be simplified in arrangement and a undesirable charge can be prevented from being mixed into a signal charge.

Claims

1. A charge-coupled device (CCD) imager comprising:

a) a CCD image sensor;

b) a horizontal register for delivering an image signal from said CCD image sensor, said horizontal register being formed of an effective bit portion corresponding to said CCD image sensor and first and second dummy bit portions of a predetermined length, said first and second dummy bit portions being located at both sides of said effective bit portion; and

first and second output portions provided in succession to said first and second dummy bit portions to provide a positive image signal and a mirror image signal, wherein said effective bit portion is connected with four bus lines through which a transfer clock is supplied to said horizontal register and said first and second dummy bit portions are each connected with only two of said four bus lines through which a transfer clock is supplied to said horizontal register.

2. The CCD imager according to claim 1, wherein said horizontal register is formed of a two-phase drive CCD.

3. The CCD imager according to claim 1, wherein the number of bits of said effective bit portion corresponds to the number of pixels of said CCD image sensor in the horizontal direction and the number of each of bits of said first and second dummy bit portions is 16 bits.

4. The CCD imager according to claim 1, wherein said transfer clocks are first and second drive pulses the phases of which are different.

5. The CCD imager as claimed in claim 1, wherein each of said effective bit portion and first and second dummy bit portions is formed of a number of first storage electrodes, first transfer electrodes, second storage electrodes and second transfer electrodes arranged repeatedly.

6. The CCD imager as claimed in claim 1, wherein the first storage electrodes in said effective bit portion are connected together by a first bus line, the first transfer electrodes in said effective bit portion, the first storage and transfer electrodes in said first dummy bit portion, and the first storage electrodes and the second transfer electrodes in said second dummy bit portion are connected together by a second bus line, the second storage electrodes in said effective bit portion are connected together by a third bus line, and the second transfer electrodes in said effective bit portion, the second storage and transfer electrodes in said first dummy bit portion, and the first transfer electrodes and the second storage electrodes in said second dummy bit portion are connected together by a fourth bus line.

7. The CCD imager as claimed in claim 6, wherein first, second, third and fourth drive signal input terminals are led out from said first, second, third and fourth bus lines, respectively.