Routing system and method for integrated circuits

• US 5,072,402 A
• Filed: 10/10/1989
• Issued: 12/10/1991
• Est. Priority Date: 10/10/1989
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Mody, Rajiv C., Ashtaputre, Sunil V.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/419,041
• Time in Patent Office: 791 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/130
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A system and method for routing interconnections through the layout of an integrated circuit is used in conjunction with a sliceable circuit layout specification that specifies the regions of the layout occupied by circuit components, a specification of the locations of terminals in the layout, and a netlist specifying for each terminal the set of other terminals that are to be connected to it. The regions of the circuit layout not occupied by circuit components are called routing regions. The circuit layout is sequentially sliced, defining a series of rectangular channels, each of which divides a region of the circuit layout containing two or more circuit components into two circuit regions each having at least one circuit component. For each channel, if there are one or more neighboring indented routing regions, a special channel is defined for each such indentation. After the entire routing region is divided into channels and special channels, interconnections are routed through those channels and special channels. In particular, before routing interconnections through each channel, interconnections are routed through the corresponding special channels, if any. A data structure is defined for denoting the sequence in which the channels are defined, the region of the layout occupied by each channel, and for each channel, the region of said layout occupied by each corresponding special channel, if any. The order in which channels are routed corresponds to the sequence in which channels were defined, as denoted in the data structure.

Claims

1. A method of routing interconnections through the layout of a circuit, the steps of the method comprising:

(a) providing a circuit layout specification including a specification of the regions of the layout occupied by circuit components, a specification of the locations of terminals in said layout, and a netlist specifying for each said terminal the set of other ones of said terminals that are to be connected to said terminal;

the regions of said circuit layout not occupied by circuit components comprising routing regions;

(b) sequentially defining a series of rectangular channels, each of which divides a region of said circuit layout containing two or more circuit components into two smaller circuit regions adjacent said rectangular channel, each of said two smaller circuit regions having at least one circuit component;

(c) for each said channel, determining for each of its two adjacent circuit regions whether there is a rectangular indentation adjacent said channel which is adjacent one side and one corner of said channel and which extends the full length of said adjacent circuit region in a direction perpendicular to said one side of said channel, and then defining a rectangular special channel for each indentation adjacent said channel, if any; and

(d) then routing interconnections through said channels and special channels;

said routing step for each said channel including the step of routing interconnections through said special channels, if any, corresponding to said channel before routing interconnections through said channel.

2. The method of routing interconnections set forth in claim 1, including the steps of

defining a data structure denoting the sequence in which said channels are defined, the region of said layout occupied by each said channel, and for each said channel, the region of said layout occupied by each corresponding special channel, if any;

said routing step including the step of routing interconnections through said channels, in an order corresponding to the sequence in which said channels were defined.

3. The method of routing interconnections set forth in claim 2, wherein said data structure comprises a routing tree having a multiplicity of nodes coupled to one another by branches, each node of said routing tree denoting the regions of said layout occupied by one said channel and its corresponding special channels, if any;

each said branch coupling a first node corresponding to a first one of said channels to a second node corresponding to a channel in one of said two circuit regions divided by said first one of said channels;

said routing tree including a root node denoting the first channel defined in step (b) and its corresponding special channels defined in step (c);

said routing step including the step of routing interconnections through said channels in an order such that each channel is routed after all other channels denoted by nodes in said routing tree which branch from said channel have been routed.

4. The method of routing interconnections through the layout of an integrated circuit, the steps of the method comprising:

(a) providing a sliceable circuit layout specification including a specification of the regions of the layout occupied by circuit components, a specification of the locations of terminals in said layout, and a netlist specifying for each said terminal the set of other ones of said terminals that are to be connected to said terminal;

the regions of said circuit layout not occupied by circuit components comprising routing regions;

(b) selecting a first slice through said circuit layout and thereby dividing said circuit layout into two circuit regions;

(c) defining a first rectangular channel corresponding to said first slice;

(d) determining for each of said two circuit regions whether there is a rectangular indentation adjacent said first channel which is adjacent one side and one corner of said channel and which extends the full length of said circuit region in a direction perpendicular to said one side of said first channel, and then defining a rectangular special channel for each indentation adjacent said first channel, if any;

(e) for each said circuit region containing at least two circuit components, performing the steps of;

(e1) selecting a slice through said circuit region and thereby dividing said circuit region into two smaller circuit regions;

(e2) defining a rectangular channel corresponding to said slice; and

(e3) determining for each of said two smaller circuit regions whether there is a rectangular indentation adjacent said channel which is adjacent one side and one corner of said channel and which extends the full length of said smaller circuit region in a direction perpendicular to said one side of said channel, and then defining a rectangular special channel for each indentation adjacent said channel, if any;

(f) repeating said steps e1, e2 and e3 until all the circuit regions have been divided into circuit regions contain only one circuit component; and

(g) then routing interconnections through said channels, in an order corresponding to the order in which said channels were defined by said channel defining steps;

said routing step for each said channel including the step of routing interconnections through said special channels, if any, corresponding to said channel before routing interconnections through said channel.

5. The method of routing interconnections set forth in claim 4, including the steps of

defining a routing tree having a root node denoting first channel and said corresponding special channels, if any;

defining a new node on said routing tree for each slice selected by step el, said node denoting said channel defined by step e2 and said corresponding special channels defined by step e3, if any;

the parent node of each said new node being a previously defined node of said routing tree corresponding to the slice which created the circuit region in which said channel for said new node is located.

6. A computer aided design system for designing interconnections between components in the layout of a circuit, comprising:

means for providing a circuit layer specification including a specification of the regions of the layout occupied by circuit components, a specification of the locations of terminals in said layout, and a netlist specifying for each said terminal the set of the other ones of said terminals that are to be connected to said terminal;

the regions of said circuit layout not occupied by circuit components comprising routing regions;

channel defining means for sequentially defining a series of rectangular channels, each of which divides a region of said circuit layout containing two or more circuit components into two smaller circuit regions each having at least one circuit component;

said channel defining means including special channel defining means for determining for each of said two smaller circuit regions whether there is a rectangular indentation adjacent said channel which is adjacent one side and one corner of said channel and which extends the full length of said smaller circuit region in a direction perpendicular to said one side of said channel, and then defining, for each said channel, a rectangular special channel for each indentation adjacent said channel, if any; and

routing means for routing interconnections through said channels and special channels;

said routing means including means for routing interconnections through said special channels, if any, corresponding to a channel before routing interconnections through said channel.

7. The computer aided design system set forth in claim 6, said channel routing means including means for defining a data structure denoting the sequence in which said channels are defined, the region of said layout occupied by each said channel, and for each said channel, the region of said layout occupied by each corresponding special channel, if any;

said routing means including means for routing interconnections through said channels, in an order corresponding to the sequence in which said channels were defined as denoted in said data structure.

8. The computer aided design system set forth in claim 7, wherein said data structure comprises a routing tree having a multiplicity of nodes coupled to one another by branches, each node of said routing tree denoting the regions of said layout occupied by one said channel and its corresponding special channels, if any;

each said branch coupling a first node corresponding to a first one of said channels to a second node corresponding to a channel in one of said two circuit regions divided by said first one of said channels;

said routing tree including a root node denoting the first channel defined by said channel means and its corresponding special channels defined by said special channel means;

said routing means including means for routing interconnections through said channels in an order such that each channel is routed after all other channels denoted by nodes in said routing tree which branch from said channel have been routed.