Dynamic random access memory with enhanced sense-amplifier circuit

  • US 5,084,842 A
  • Filed: 06/12/1990
  • Issued: 01/28/1992
  • Est. Priority Date: 06/13/1989
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • a substrate;

    parallel bit lines provided on said substrate;

    parallel word lines insulatively crossing said bit lines above said substrate to define cross points therebetween;

    memory cells provided at the cross points, each of said memory cells having a data storage capacitor and a transistor;

    sense amplifier means connected to said bit lines, for sensing a data voltage; and

    discharge control means, associated with said sense amplifier means, for forming a discharge path branched between said bit lines and a ground potential when a certain word line is specified and a memory cell is selected from those memory cells connected to said certain work line, thereby progressing discharging of charges.

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