Non-binary memory array

• US 5,093,805 A
• Filed: 06/20/1990
• Issued: 03/03/1992
• Est. Priority Date: 06/20/1990
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Singh, Gurdev
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/541,122
• Time in Patent Office: 622 Days
• Field of Search: 365/51, 365/200, 365/189.01, 365/230.01, 365/230.06, 365/221, 365/73, 365/78, 365/239
• US Class Current: 365/51
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

An integrated circuit device having a memory array of memory cells in which the total number N of unique available memory addresses is a power of two, yet wherein neither the number of columns nor the number of rows of cells is a power of two. This permits the chip die size and height/width ratio to be optimized. The device further includes a circuitry for generating address selection signals, providing a total number of unique addresses equal to N, leaving unused some of the memory cells comprising the array.

Claims

1. In an integrated semiconductor circuit device fabricated on a semiconductor chip die, an addressable memory array circuit characterized by N uniquely addressable address locations, wherein N is an integral power of two, comprising:

a two-dimensional memory array comprising a primary plurality of memory cells arranged in R rows and C columns, and wherein, exclusive of any redundant rows or columns of cells used to replace defective cells of said primary plurality of memory cells, neither R nor C is an integral power of two, wherein the number of memory cells of said primary plurality of memory cells comprising said array is not an integral power of two; and

means for generating internal array addressing signals to select a unique address location for a cell or group of cells comprising said array, said means providing the capability of selecting only a number N of said cells or groups of cells comprising the array,

thereby permitting the height/width ratio of the die to be optimized.

2. The circuit of claim 1 wherein said circuit is a randomly accessible memory (RAM) circuit responsive to memory address selection signals, and said means for generating addressing signals comprises a means for mapping said memory address selection signals into address signals which select the particular row and column at which the desired address location is located.

3. The circuit of claim 2 wherein said circuit further comprises means for reading data from a memory cell or group of cells in accordance with the address location determined by said memory address selection signal.

4. The circuit of claim 1 wherein said circuit comprises a first-in-first-out memory buffer circuit, and said means for generating internal array addressing signals comprises a first means for generating internal sequential write address signals, and second means for generating internal sequential read address signals.

5. An integrated circuit device having a memory array of memory cells arranged in rows and columns, wherein the number of available cell word locations N is a power of two, and a means for generating internal sequential addresses, further characterized in that:

said array is defined by a number of rows R and a number of columns C of memory cells, wherein neither R nor C is a power of two; and

said means for generating internal sequential addresses comprises an array address counter having a total number of different unique count states equal to N, said array address counter comprising;

a column counter whose state determines the unique column address, said column counter having a total number of possible unique states equal to the number of unique column addresses C, said column counter generating a column signal when the counter state reaches the maximum count state;

a row counter incremented by said column counter signal and having a maximum number of unique count states at least equalling the number of unique row addresses R, the state of said row counter determining the unique row address; and

means responsive to the column and row counter states for detecting when the internal address has been incremented N times and generating an array address reset signal which resets the column and row counter states to zero.

6. The integrated circuit device of claim 5 wherein data words are loaded into said memory array under control of a write control signal, said array address counter being responsive to said write control signal to increment the state of said column counter.

7. The integrated circuit device of claim 5 wherein data words are read from said memory array under control of a read control signal, said array address counter being responsive to said read control signal to increment the state of the column counter.

8. The integrated circuit device of claim 5 wherein said array address counter has sequential count states from zero to (N-1), and wherein said detecting means comprises means for detecting when the array address count state reaches the value (N-1).

9. The integrated circuit device of claim 5 wherein said row counter comprises a binary counter circuit.

10. An integrated first-in-first-out (FIFO) memory circuit device having a memory array of memory cells arranged in rows and columns, wherein the number of available cell word locations N is a power of two, and a means for generating internal write sequential addresses, further characterized in that:

said array is defined by a number of rows R and a number of columns C of memory cells, wherein neither R nor C is a power of two, and wherein the total number of unique array addresses N employed by the device is a power of two;

said means for generating internal write sequential addresses comprises a write address counter having a total number of different unique count states equal to N, said address write counter comprising;

a write column counter whose state determines the unique write column address, said column counter having a total number of possible unique states equal to the number of unique column addresses C, said write column counter generating a write column signal when the counter state reaches the maximum count state;

a write row counter incremented by said write column signal and having a maximum number of unique count states at least equalling the number of unique row addresses R, the state of said write row counter determining the unique write row address; and

means responsive to the column and row counter states for detecting when the internal write address has been incremented N times and generating a write a rest signal which resets the write column and row counter states to zero; and

said mean for generating internal read sequential

addresses comprises a read address counter having a total number of different unique count states equal to N, said read counter comprising;

a read column counter whose state determines the unique read column address, said column counter having a total number of unique column addresses C, said read column counter generating a read column signal when the counter state reaches the maximum count state;

a read row counter incremented by the read column signal and having a maximum number of unique count states at least equaling the number of unique row addresses R, the state of said read row counter determining the unique read row address; and

means responsive to the read column and row counter states for detecting when the internal write address has been incremented N times, and generating a read reset signal which resets the read column and row counter states to zero.

11. The FIFO memory device of claim 10 wherein said write row counter comprises a binary counter circuit.

12. The FIFO memory device of claim 10 wherein said read row counter comprises a binary counter circuit.

13. In an integrated semiconductor circuit device comprising a first-in, first-out memory buffer circuit, an addressable memory array circuit characterized by N uniquely addressable address locations, wherein N is an integral power of two, comprising:

a memory array comprising a plurality of memory cells arranged in R rows and C columns, wherein neither R nor C is an integral power of two, wherein the number of memory cells of the array is not an integral power of two; and

means for generating internal array addressing signals to select a unique address location for a cell or group of cells comprising said array, said means providing the capability of selecting only a number N of said cells or groups of cells comprising the array, and wherein said means comprises a first means for generating internal sequential write address signals, and second means for generating internal sequential read address signals.