Phase-difference detecting circuit and method of reducing power consumption in a PLL system

• US 5,103,192 A
• Filed: 06/06/1990
• Issued: 04/07/1992
• Est. Priority Date: 06/14/1989
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Kyushu Fujitsu Electronics Ltd. (Fujitsu Limited)
• Inventors: Sekine, Shinichi, Kamizono, Yukinori, Asami, Fumitaka
• Primary Examiner(s): Pascal, Robert J.
• Application Number:
  US07/534,618
• Time in Patent Office: 671 Days
• Field of Search: 331/1 A, 331/25, 307/514, 307/516, 307/525, 307/526, 307/527, 307/528, 328/133, 328/134, 328/155, 455/343, 455/76
• US Class Current: 331/1.00A
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A phase comparison circuit includes phase comparison device for generating an output signal corresponding to the difference in phase between a first input signal and a second input signal. The phase comparison device has an active mode, and a standby mode in which power consumption is reduced. A phase-difference detecting device is connected to the phase comparison device for outputting a control signal when the phase difference between the first and second input signals is smaller than a predetermined value. The phase comparison device is switched from the standby mode to the active mode in response to the control signal.

Claims

1. A phase comparison circuit comprising:

phase comparison means for generating an output signal corresponding to a difference in phase between a first input signal and a second input signal, the phase comparison means having an active mode, and standby mode in which power consumption is reduced, said phase comparison means comprises a first frequency divider for dividing said first input signal, a second frequency divider for dividing said second input signal, and a phase comparator to which an output of said first frequency divider and an output of said second frequency divider are input, each of said first and second frequency dividers having said standby mode to said active mode in response to a control signal; and

phase-difference detecting means connected to said phase comparison means for outputting said control signal when the phase difference between said first and second input signals is smaller than a predetermined value;

said phase comparison means being switched from said standby mode to said active mode in response to said control signal.

2. A phase comparison circuit as set forth in claim 1, wherein said phase comparator has said active mode and standby mode, and is switched from said standby mode to said active mode in response to said control signal.

3. A phase comparison circuit as set forth in claim 1, wherein said phase-difference detecting means comprises:

a first flip-flop having a data input terminal to which said first input signal is input and a clock input terminal to which said second input signal is input;

delay means for delaying said second input signal by a predetermined delay;

a second flip-flop having a data input terminal to which said first input signal is input and a clock input terminal to which an output of said delay means is input;

logic means to which said first input signal, an output of said first flip-flop, and an output of said second flip-flop are input; and

when said first flip-flop output and said second flip-flop output rise or fall within a predetermined range, a signal for informing that there is substantially no phase difference between said two outputs being output by said logic means.

4. A semiconductor interpreted circuit comprising:

phase comparison means for generating an output signal corresponding to a difference in phase between a first external input signal and a second external input signal, the phase comparison means having an active mode, and standby mode in which power consumption is reduced, said phase comparison means comprises a first frequency divider for dividing said first external input signal, a second frequency divider for dividing said second external input signal, a phase comparator to which an output of said first frequency divider and an output of said second frequency divider are input, each of said first and second frequency dividers having said active mode and standby mode and being switched from said standby mode to said active mode in response to a control signal; and

phase-difference detecting means, connected to said phase comparison means, for outputting said control signal when an external power save control signal indicates switching from said standby mode to said active mode and when said phase difference between said external first and second input signals is smaller than a predetermined value;

said phase comparison means being switched from said standby mode to said active mode in response to said control signal.

5. A semiconductor integrated circuit device as set forth in claim 4, wherein said phase comparison means has said active mode and standby mode, and is switched from said standby mode to said active mode in response to said external power save control signal.

6. A semiconductor integrated circuit device as set forth in claim 4, wherein said phase comparator has said active mode and standby mode, and is switched from said standby mode to said active mode in response to said control signal.

7. A semiconductor integrated circuit device as set forth in claim 4, wherein said phase comparison means further comprises

a first gate circuit having input terminals to which said first external input signal and said external power save control signal are input, and an output terminal connected to said first frequency divider;

and

a second gate circuit having input terminals to which second external input signal and said external power save control signal are input, and an output terminal connected to said first frequency divider;

said first and second gate circuits allowing said first and second dexternal inputs signals to pass therethrough when said external power save control signal is active, and preventing said first and second external input signals from passing therethrough when said external power save control signal is active.

8. An intermittent-operation type phase-locked loop system comprising:

a phase-locked loop circuit for generating an output signal synchronizing in phase with a reference signal, the phase-locked loop circuit having an active mode and a standby mode in which power consumption is reduced, and the phase-locked loop circuit being switched from said active mode to said standby mode in response to a power save control signal, said phase-locked loop circuit comprising a first frequency divider for dividing said reference signal, a second frequency divider for dividing said output signal, and a phase comparator to which an output of said first frequency divider and an output of said second frequency divider are input, each of said first and second frequency dividers having said active mode and said standby mode and being switched from said standby mode to said active mode in response to a control signal; and

phase-difference detecting circuit connected to said loop circuit for outputting said control signal when said power save control signal is released and when a phase difference between said reference signal and said output signal is smaller than a predetermined value;

said phase-locked loop circuit being switched from said standby mode to said active mode in response to said control signal.

9. A phase comparison circuit comprising:

a first flip-flop having a data input terminal to which a first signal with a first frequency is input and a clock input terminal to which a second signal with a second frequency is input;

delay means for delaying said second signal by a predetermined delay;

a second flip-flop having a data input to which said first signal is input and a clock input terminal to which an output of said delay means is input;

logic means to which said first signal, an output of said first flip-flop, and an output of said second flip-flop are input; and

when said first flip-flop output and said second flip-flop output rise or fall within a predetermined range, a signal for informing that therein is substantially no phase difference between said two outputs being output by said logic means.