Heterojunction bipolar transistor with a thin silicon emitter

• US 5,105,250 A
• Filed: 10/09/1990
• Issued: 04/14/1992
• Est. Priority Date: 10/09/1990
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Tam, Gordon, Knoch, Lynnita K.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): FAHMY, WAEL M
• Application Number:
  US07/594,576
• Time in Patent Office: 553 Days
• Field of Search: 357/35, 357/34, 357/16, 357/59 H
• US Class Current: 257/197
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Abstract

A heterojunction bipolar transistor having a thin, lightly doped, silicon emitter disposed on a silicon-germanium base layer exhibits low emitter resistance and low emitter-base capacitance. The lightly doped silicon emitter maintains the bandgap differential between silicon-germanium and silicon. The silicon emitter is fabricated such that the silicon emitter will be substantially depleted at zero bias, resulting in low emitter-base resistance and emitter resistance.

Claims

1. A heterojunction bipolar transistor, comprising:

a collector;

a silicon-germanium base disposed on the collector;

a thin silicon emitter disposed on the silicon-germanium base, wherein a metallurgical junction is maintained at the silicon-germanium base and the thin silicon emitter interface; and

a polysilicon layer disposed on the thin silicon emitter.

2. The heterojunction bipolar transistor of claim 1 wherein the silicon emitter is of a thickness where the thin silicon emitter is substantially depleted at zero bias.

3. The heterojunction bipolar transistor of claim 2 wherein the silicon emitter is of a thickness of approximately 500 to 2,500 angstroms.

4. A heterojunction bipolar transistor comprising:

a collector;

a silicon-germanium base formed on the collector;

a thin silicon emitter formed on the silicon-germanium base, wherein the silicon emitter has a thickness and a doping level such that it is substantially depleted during normal operation, and wherein a metallurgical junction is maintained at the silicon-germanium base and the thin silicon emitter interface; and

a polysilicon layer formed on the silicon layer.

5. The heterojunction bipolar transistor of claim 4 wherein the silicon emitter is of a thickness of approximately 500 to 2,500 angstroms.

6. The heterojunction bipolar transistor of claim 4 wherein the polysilicon layer is heavily doped.

7. A heterojunction bipolar transistor, comprising:

an N-type collector;

a P-type silicon-germanium base formed on the collector;

an N-type, thin, lightly doped silicon emitter formed on the silicon-germanium base, wherein a metallurgical junction is maintained at the P-type silicon-germanium base and the N-type, thin, lightly doped silicon emitter interface; and

an N-type, heavily doped polysilicon layer formed on the silicon layer.

8. The heterojunction bipolar transistor of claim 7 wherein the thin, lightly doped silicon emitter is substantially depleted during normal operation.

9. The heterojunction bipolar transistor of claim 8 wherein the thin, lightly doped silicon emitter is doped at approximately 8×

10¹⁶ to 3×

10¹⁷ atoms/cm³.

10. The heterojunction bipolar transistor of claim 7 wherein the heavily doped polysilicon layer is doped at approximately 1×

10¹⁹ atoms/cm³.