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Parallel processors sequentially encoding/decoding compaction maintaining format compatibility

  • US 5,109,226 A
  • Filed: 10/29/1990
  • Issued: 04/28/1992
  • Est. Priority Date: 11/22/1989
  • Status: Expired due to Term
First Claim
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1. An arithmetic binary compaction system comprising a number n of compaction processors, each compaction processor having one encoder and one decoder, with each of said encoders and decoders having m number of statistic table, each compaction processor handling an equal sized set of data for coding, wherein:

  • q=number of sets of data to be coded;

    i=set number of q;

    set i is processed by compaction processor j using the statistic table k, wherej=i modulo n, andk=(i divided by n) modulo m;

    and where for an N compaction processor system with M statistic tables in each compaction system, the configuration of a lesser than N number of compaction processors in a compaction system is defined bym is equal to or less than M, andn is equal to or less than N,with m, n, M, and N being integers greater than zero and n is the number of compaction processors used out the maximum in an N number of compaction processors in the system and m is the number of statistic tables used out of the M maximum number in each compaction processor.

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