Data processing system with system resource management for itself and for an associated alien processor

• US 5,113,522 A
• Filed: 05/17/1989
• Issued: 05/12/1992
• Est. Priority Date: 05/17/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dinwiddie, John M. Jr., Suarez, Gustavo A., Freeman, Bobby J., Sanderson, Kenneth R., Grice, Lonnie E., Loffredo, John M.
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/353,112
• Time in Patent Office: 1,091 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 713/375
• CPC Class Codes: G06F 11/1608 Error detection by comparing the output signals of redundant hardware G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: H04L 69/00 Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass networks security protocols H04L9/40; wireless communication networks H04W

Abstract

The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contigous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

Claims

1. In a data processing system of the type in which system initialization routines control the self testing and initialization of each of a first pair and a second partner pair of processors and their respective associated hardware, in which each pair of processors and its associated hardware is kicked off into lock step operation with the other pair upon satisfactory self testing and initialization, and in which the pairs of processors and their hardware thereafter perform identical operations in lock step under control of a first operating system and programs having a first instruction architecture, the improvement comprising

an additional first pair of processors and an additional partner pair of processors each pair adapted to perform identical operations under control of a second operating system and programs having a second instruction architecture,

means for directly coupling each processor of the additional pairs to a respective processor of the first and second partner pair,

logic means controlled by application program instructions running on the first and second partner pairs of processors for uncoupling the first and second partner pairs of processors from their associated hardware and concurrently coupling the first and second partner pairs of processors to respective processors in the additional pairs via said direct coupling means for the transfer of commands and data therebetween,

application program controlled means associated with the first and second partner pairs of processors for initiating and controlling the self testing and initialization of the additional pairs of processors via commands and data applied to said direct coupling means while the first pair of processors are uncoupled from their hardware,

second logic means effective during system initialization for inhibiting the kick off of the first and second partner pairs of processors into lock step operation until the additional pairs of processors are self tested and initialized in a manner indiscernible to the first operating system, and

means initiating the concurrent kick off of the first and second partner pairs of processors and the kick off of said additional first and partner pairs of processors in lock step operation upon completion of all self testing and initializing in a manner indiscernible to the first operating system.

2. The system of claim 1 further comprising a first clock means for the first pair of processors, a second clock means for the second pair of processors, and

logic means synchronizing the second clock means with the first clock means for the effective transfer of commands and data between the first and second pairs of processors.

3. In a data processing system of the type in which system initialization routines control the self testing and initialization of each of a first pair and a second partner pair of processors, in which each pair of processors is kicked off into lock step operation with the other pair upon satisfactory self testing and initialization, and in which the pairs of processors thereafter perform identical operations in lock step under control of a first operating system and programs having a first instruction architecture, the improvement comprising

an additional first pair of processors and an additional partner pair of processors each pair adapted to perform identical operations under control of a second operating system and programs having a second instruction architecture,

means effective during system initialization for inhibiting the kick off of the first and second partner pairs of processors into lock step operation until the additional pairs of processors are self tested and initialized in a manner indiscernible to the first operating system,

application program controlled means associated with the first and second partner pairs of processors for initiating and controlling the self testing and initialization of the additional pairs of processors in a manner indiscernible to the first operating system, and

means initiating the concurrent kick off of the first and second partner pairs of processors and the kick off of said additional first and partner pairs of processors in lock step operation upon completion of all self testing and initializing in a manner indiscernible to the first operating system.

4. The system of claim 3 further comprising a first clock means for the first pair of processors, a second clock means for the second pair of processors, and

logic means synchronizing the second clock means with the first clock means for the effective transfer of commands and data between the first and second pair of processors.

5. In a data processing system including at least one processor, main storage, and input/output devices operated under control of a first operating system and providing at least certain of the services such as resource allocation, scheduling, storage management, input/output control, error detection/isolation and recovery, dynamic reconfiguration and data management for the system, and further including configuration tables identifying the system resources for the operating system, in combination therewith

a second system including at least a second processor operating under control of a second operating system, said resource configuration tables lacking data identifying the second system, and

means coupling the one and second processors to each other, and

means associated with the first-mentioned system for initiating and controlling and/or re-initiating and controlling at least certain of said services for said second system without utilizing said first operating system and in a manner indiscernible by said first operating system.

6. The combination set forth in claim 5 wherein said initiating and controlling means includes

application program routines adapted to run in said first-mentioned system.

7. The combination set forth in claim 6 wherein said initiating and controlling means further includes

logic means uncoupling the one processor from the first-mentioned system and coupling said one processor to said coupling means under control of the application program routines for passing commands and data between the processors without utilizing the services of said first operating system.

8. In a fault tolerant data processing system of the type in which a first pair of fault tolerant processors of one architecture perform identical operations concurrently under control of a first operating system, in which a second partner pair of fault tolerant processors of said one architecture perform said identical operations concurrent with the first pair under said first operating system control, in which the processor pairs are coupled to duplicated identical system buses and to paired fault tolerant I/O devices and paired fault tolerant main storage units via said buses for the transfer of identical data between the paired processor, I/O devices and main storage units under said operating system control, in which signals applied to the system buses by each pair of processors are periodically compared for error detection, in which means responsive to the detection of an error removes from service an error causing pair of processors to permit continued operation of the system with the remaining processor pair and in which reconfiguration means are provided for testing the error causing pair of processors and returning them to service in the event that the detected error no longer exists, in combination therewith

an additional first pair and an additional partner pair of processors having an architecture different from said one architecture, coupled to said system buses, and performing identical operations concurrently with each other under control of a second operating system,

additional means periodically comparing signals applied to the system buses by each additional pair of processors of detecting errors;

means including the processors in the first pair and second partner pair for passing I/O commands and data from the processors in the additional first pair and additional partner pair of respective processors in the first pair and second partner pair in a manner indiscernible to the first operating system;

means converting said commands and data to commands executable by and data useable by said processors of the first pair and second partner pair to permit the first pair of processors and the second partner pair of processors to act as I/O controllers for respective ones of the additional first pair of processors and the additional partner pair of processors;

means associated with the processors of said first pair and said second partner pair selectively removing from service one of said additional pairs of processors and its respective processors in the first pair of second partner pair when an error is detected in signals applied by either said one additional pair of processors or its respective processors in the first pair or second partner pair to the system buses and continuing operation of the other pairs, thereby rendering said additional pairs of processors fault tolerant; and

means including said reconfiguration means for testing said pairs of processors which are removed from service and returning them to service in the event that the detected error no longer exists.