Avoiding spin-on-glass cracking in high aspect ratio cavities

• US 5,119,164 A
• Filed: 02/05/1991
• Issued: 06/02/1992
• Est. Priority Date: 07/25/1989
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sliwa, John W. Jr., Dixit, Pankaj
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Monin, D.
• Application Number:
  US07/652,306
• Time in Patent Office: 483 Days
• Field of Search: 357/71, 357/73, 357/54, 357/68, 437/195
• US Class Current: 257/776
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Before spin-on-glass (SOG) is applied and soft-cured over metal traces (10) having a height/width aspect ratio (of the spaces) of at least 1, the aluminum metal traces are selectively coated with selective tungsten (16). After SOG (18) is spun on and soft-cured, it is etched back to expose the metal interconnects. A selective tungsten wet etch in H₂ O₂ detaches the SOG from the metal walls, leaving silt-like voids (20). Stress-free SOG hard curing may now proceed. A capping layer (22) of SOG may now be applied, soft-cured, then hard-cured. Alternatively, other dielectric materials may be applied as the capping layer. Further, interfacial lateral sidewall voids (24) may be deliberately left unfilled, by employing a capping layer (24'"'"') of vapor-deposited oxide. The unfilled voids have a dielectric constant of 1.0, which is useful in extremely high speed devices. The resulting structure is comparatively stress-free as fabricated and is resistant to later environmentally-induced brittle tensile fracture.

Claims

1. An integrated circuit containing a plurality of low-resistivity metal interconnect layers in which at least two of said adjacent layers are electrically isolated and separated from each other by a cavity having a height H and a width W and occupied by a first layer of a dielectric material consisting essentially of spin-on-glass partially detached from adjacent interconnect sidewalls and by a second layer of a dielectric material which covers the top of said interconnects and fills at least a portion of a region between said first layer and said sidewalls, leaving a region of closed space located interfacially on said sidewalls, said region having a dielectric constant approximately equal to 1, thereby permitting use of cavities having an aspect ratio of H/W of at least about 1 between said interconnects.

2. The integrated circuit of claim 1 wherein said aspect ratio is greater than 1.

3. The integrated circuit of claim 1 wherein said second layer of dielectric is selected from the group consisting of CVD and PVD oxide.