Semiconductor memory

• US 5,119,332 A
• Filed: 04/30/1990
• Issued: 06/02/1992
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Shimohigashi, Katsuhiro, Kawamoto, Hiroshi, Masuda, Hiroo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/515,345
• Time in Patent Office: 764 Days
• Field of Search: 365/189.01, 365/189.05, 365/189.07, 365/205, 365/186, 365/190, 365/149
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at the cross point thereof;

selecting means coupled to said plurality of word lines including means for placing one of said plurality of word lines in a selected state;

amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines, said amplifier comprising first and second circuits;

said first circuit including a pair of cross-coupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation; and

said second circuit including a pair of cross-coupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation,

wherein the differential amplification operation of said cross-coupled N-channel MISFETs is started at a time different from the time when the differential amplification operation of said cross-coupled P-channel MISFETs is started.

2. A semiconductor memory according to claim 1, further comprising a first terminal coupled to a source side of said cross-coupled N-channel MISFETs and supplied with a first reference voltage and a second terminal coupled to a source side of said cross-coupled P-channel MISFETs and supplied with a second reference voltage.

3. A semiconductor memory according to claim 2, wherein the differential amplification operation of said cross-coupled N-channel MISFETs is started in response to said first reference voltage being supplied to said source side of said cross-coupled N-channel MISFETs, and wherein the differential amplification operation of said cross-coupled P-channel MISFETs is started in response to said second reference voltage being supplied to said source side of said cross-coupled P-channel MISFETs.

4. A semiconductor memory according to claim 3, further comprising precharging means for setting said pair of data lines at a potential intermediate between said first reference voltage and said second reference voltage.

5. A semiconductor memory according to claim 4, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cells.

11. A semiconductor memory according to claim 3, further comprising an N-channel MISFET coupled between said first terminal and said first reference voltage for controlling the differential amplification operation of said cross-coupled N-channel MISFETs, and a P-channel MISFET coupled between said second terminal and said second reference voltage for controlling the differential amplification operation of said cross-coupled P-channel MISFETs.

12. A semiconductor memory according to claim 5, further comprising an N-channel MISFET coupled between said first terminal and said first reference voltage for controlling the differential amplification operation of said cross-coupled N-channel MISFETs, and a P-channel MISFET coupled between said second terminal and said second reference voltage for controlling the differential amplification operation of said cross-coupled P-channel MISFETs.

6. A semiconductor memory comprising:

a pair of data lines which extend substantially in parallel to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said data lines; and

a sense amplifier for amplifying a difference between signal levels appearing on said pair of data lines when a stored signal of one of said memory cells is read out, said amplifier comprising first and second circuits,

wherein said first circuit is coupled to a first end side of said pair of data lines while said second circuit is coupled to a second end side of said pair of data lines opposite said first end side so that said memory cells are located between said first and second circuits, and

wherein said first circuit includes a pair of cross-coupled N-channel transistors, and wherein said second circuit includes a pair of cross-coupled P-channel transistors,

further including;

a first MISFET coupled on a source side of said cross-coupled N-channel transistors for controlling a differential amplification operation of said cross-coupled N-channel transistors; and

a second MISFET coupled on a source side of said cross-coupled P-channel transistors for controlling a differential amplification operation of said cross-coupled P-channel transistors.

7. A semiconductor memory comprising:

a pair of data lines which extend substantially in parallel to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said data lines; and

a sense amplifier for amplifying a difference between signal levels appearing on said pair of data lines when a stored signal of one of said memory cells is read out, said amplifier comprising first and second circuits,

wherein said first circuit is coupled to a first end side of said pair of data lines while said second circuit is coupled to a second end side of said pair of data lines opposite said first end side so that said memory cells are located between said first and second circuits, and

wherein said first circuit includes a pair of N-channel MISFETs, each of which has a gate terminal coupled to a drain terminal of the other MISFET of said pair of N-channel MISFETs and the drain terminal coupled to one of said pair of data lines, and wherein said second circuit includes a pair of P-channel MISFETs, each of which has a gate terminal coupled to a drain terminal of the other MISFET of said pair of P-channel MISFETs and the drain terminal coupled to one of said pair of data lines.

8. A semiconductor memory according to claim 7, further including:

a first MISFET coupled on a source side of said pair of N-channel MISFETs for controlling a differential amplification operation of said pair of N-channel MISFETs; and

a second MISFET coupled on a source side of said pair of P-channel MISFETs for controlling a differential amplification operation of said pair of P-channel MISFETs.

9. A semiconductor memory comprising:

a memory cell array having a plurality of pairs of data lines which extend between opposite end areas of said memory cell array, a plurality of word lines which extend in a direction traversing said plurality of pairs of data lines, and a plurality of memory cells arrayed in association with said data and word lines; and

a plurality of sense amplifiers, each of which is coupled to each pair of data lines for amplifying a difference between signal levels appearing on the pair of data lines,

wherein said each sense amplifier includes a pair of N-channel MISFETs coupled to said pair of data lines formed in one end area of said memory cell array and a pair of P-channel MISFETs coupled to said pair of data lines formed in the other end area of said memory cell array, and

wherein each one of said N-channel MISFETs has a gate terminal coupled to a drain terminal of the other MISFET of said pair of N-channel MISFETs and the drain terminal coupled to one of said pair of data lines, and wherein each one of said P-channel MISFETs has a gate terminal coupled to a drain terminal of the other MISFET of said pair of P-channel MISFETs and the drain terminal coupled to one of said pair of data lines.

13. A semiconductor memory according to claim 9, wherein said N-channel MISFETs of each of said sense amplifiers are coupled to the corresponding pair of data lines to bring about a differential amplification operation, wherein said P-channel MISFETs of each of said sense amplifiers are coupled to the corresponding pair of data lines to bring about a differential amplification operation, and wherein the differential amplification operation of said N-channel MISFETs is started at a time different from the time when the differential amplification operation of said P-channel MISFETs is started.

15. A semiconductor memory according to claim 13, further comprising a first terminal coupled to a source side of said N-channel MISFETs and supplied with a first reference voltage and a second terminal coupled to a source side of said P-channel MISFETs and supplied with a second reference voltage.

16. A semiconductor memory according to claim 15, wherein the differential amplification operation of said N-channel MISFETs is started in response to said first reference voltage being supplied to said source side of said N-channel MISFETs, and wherein the differential amplification operation of said P-channel MISFETs is started in response to said second reference voltage being supplied to said source side of said P-channel MISFETs.

17. A semiconductor memory according to claim 16, further comprising precharging means for setting said pairs of data lines at a potential intermediate between said first reference voltage and said second reference voltage.

18. A semiconductor memory according to claim 17, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cells.

19. A semiconductor emory according to claim 16, further comprising an additional N-channel MISFET coupled between said first terminal and said first reference voltage for controlling the differential amplification operation of said N-channel MISFETs, and an additional P-channel MISFET coupled between said second terminal and said second reference voltage for controlling the differential amplification operation of said P-channel MISFETs.

10. A semiconductor memory comprising:

a pair of data lines which extend substantially in parallel to each other;

a plurality of word lines traversing said pair of data lines;

a pair of N-channel MISFETs and a pair of P-channel MISFETs coupled by connecting nodes to said pair of data lines, respectively, for amplifying a difference between signal levels appearing on said pair of data lines; and

a plurality of memory cells, each of which is coupled by connecting nodes to one of said word lines and one of said data lines;

wherein connecting nodes of said plurality of memory cells and said data lines are arranged between connecting nodes of said N-channel MISFETs and said data lines and connecting nodes of said P-channel MISFETs and said data lines, and

wherein each one of said N-channel MISFETs has a gate terminal coupled to a drain terminal of the other MISFET of said pair of N-channel MISFETs and a drain terminal coupled to one of said pair of data lines, and wherein each one of said P-channel MISFETs has a gate terminal coupled to a drain terminal of the other MISFET of said pair of P-channel MISFETs and a drain terminal coupled to one of said pair of data lines.

14. A semiconductor memory according to claim 10, wherein said pair of N-channel MISFETs are coupled to the pair of data lines to bring about a differential amplification operation, wherein said pair of P-channel MISFETs are coupled to the pair of data lines to bring about a differential amplification operation, and wherein the differential amplification operation of said N-channel MISFETs is started at a time different from the time when the differential amplification operation of said P-channel MISFETs is started.

20. A semiconductor memory according to claim 14, further comprising a first terminal coupled to a source side of said N-channel MISFETs and supplied with a first reference voltage and a second terminal coupled to a source side of said P-channel MISFETs and supplied with a second reference voltage.

21. A semiconductor memory according to claim 20, wherein the differential amplification operation of said N-channel MISFETs is started in response to said first reference voltage being supplied to said source side of said N-channel MISFETs, and wherein the differential amplification operation of said P-channel MISFETs is started in response to said second reference voltage being supplied to said source side of said P-channel MISFETs.

22. A semiconductor memory according to claim 21, further comprising precharging means for setting said pair of data lines at a potential intermediate between said first reference voltage and said second reference voltage.

23. A semiconductor memory according to claim 22, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cells.

24. A semiconductor memory according to claim 21, further comprising an additional N-channel MISFET coupled between said first terminal and said first reference voltage for controlling the differential amplification operation of said N-channel MISFETs, and an additional P-channel MISFET coupled between said second terminal and said second reference voltage for controlling the differential amplification operation of said P-channel MISFETs.