Register bus multiprocessor system with shift

• US 5,119,481 A
• Filed: 04/26/1991
• Issued: 06/02/1992
• Est. Priority Date: 12/22/1987
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Kendall Square Research Corp.
• Inventors: Frank, Steven J., Weber, Frederick D., Burkhardt, Henry III
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US07/696,291
• Time in Patent Office: 403 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/85.1, 370/85.15, 370/60, 370/61, 370/91, 370/94.1
• US Class Current: 710/100
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion

Abstract

A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

Claims

1. A digital data processing apparatus comprising

A. bus means for transferring packets of information-representative digital signals, said bus means including shift register means comprising a plurality of digital storage and transfer stages connected in series in a ring configuration for sequentially storing and transferring said information-representative digital signals, wherein each said stage within said shift register means includes means for storing an information-representative signal of (M) bits, where (M) is greater than one,

B. a plurality of processing cells, connected in a ring configuration through said bus means, each processing cell being in communication with an associated subset of (N) said stages, where (N) is greater than one, at least one of said cells having associated memory means coupled thereto for storing a plurality of information-representative digital signals.

C. said at least one said processing cell further including cell interconnect means, connected to said associated subset of stages and said associated memory means, for selectively transferring information-representative signals between said associated subset of stages and said associated memory means,

D. said cell interconnect means including means for performing at least one of modifying, extracting, replicating and transferring a packet of digital information-representative signals, wherein at least a portion of said packet is stored within said associated subset of stages, based on an association, if any, between an information-representative signal identified in that packet and one or more information-representative signals of said plurality of information-representative signals stored in said associated memory means, and

E. said cell interconnect means including means responsive to applied digital clock cycle signals for simultaneously transferring at least a selected digital signal packet through successive stages of said associated subset o stages, at a rate responsive to said digital clock cycle rate, while performing said at least one modifying, extracting, replicating and transferring operation on that same digital signal packet.

2. A digital data processing apparatus according to claim 1, wherein said at least one processing cell includes

A. directory means for storing signals representative of one or more information-representative digital signals of said plurality of information-representative signals stored in said associated memory means,

B. means coupled with said cell interconnect means and with said directory means for generating a cell interconnect control signal based on a comparison of said information-representative signal identified in said packet with those represented in said directory means, and

C. said cell interconnect means includes means selectively responsive to said cell interconnect control signal for performing said at least one modifying, extracting, replicating and transferring operation on said digital signal packet.

4. A data processing apparatus according to any of claims 1 - 3, wherein said at least one processing cell includes

A. means for generating and transmitting to the associated cell interconnect means a cell interconnect control signal representative of a packet store request, and

B. said associated cell interconnect means includes means responsive to said packet store request signal for storing a selected information-representative signal to an associated stage of said shift register means.

5. A data processing apparatus according to any of claims 1 - 3, wherein said at least one processing cell includes

A. means for generating and transmitting to the associated cell interconnect means a cell interconnect control signal representative of a packet access request, and

B. said associated cell interconnect means includes means responsive to said packet access request signal for providing said processing cell access to an information-representative signal stored in an associated stage of said shift register means.

6. A data processing apparatus according to any of claims 1 - 4, wherein said at least one processing cell includes

A. means for generating and transmitting to the associated cell interconnect means a cell interconnect control signal representative of a packet extraction request, and

B. said associated cell interconnect means includes means responsive to said packet extraction request signal for extracting an information-representative signal stored in an associated stage of said shift register means and for transferring that extracted information-representative signal to said associated processing cell.

7. A data processing apparatus according to any of claims 1 - 3, wherein said at least one processing cell includes

A. means for generating and transmitting to the associated cell interconnect means a cell interconnect control signal representative of a packet replication request, and

B. said associated cell interconnect means includes means responsive to said packet replication request signal for replicating an information-representative signal stored in an associated stage of said shift register means and for transferring that replicated information-representative signal to said associated processing cell.

8. A data processing apparatus according to any of claims 1 - 3, wherein said at least one processing cell includes

A. means for generating and transmitting to the associated cell interconnect means a cell interconnect control signal representative of a packet transfer request, and

B. said associated cell interconnect means includes means responsive to said packet transfer request signal for transferring unchanged and information-representative signal stored in a first associated stage of said shift register means to a second, succeeding associated stage of said shift register means.

9. A data processing apparatus according to any of claims 1 - 3, wherein said at least one processing cell includes

A. means for generating and transmitting to the associated cell interconnect means a cell interconnect control signal representative of a packet identify request, and

B. said associated cell interconnect means includes means responsive to said packet identify request signal to identify a given digital information-representative signal stored in an associated stage of said shift register means as the first information-representative signal of a digital signal packet.

10. A digital data processing apparatus according to claim 9, wherein said cell interconnect means includes

A. means for generating and transmitting to the associated cell interconnect means a cell interconnect control signal representative of a packet identify command, and

B. said cell interconnect means includes means responsive to said packet identify command signal for setting a digital information-representative signal stored in an associated stage of said shift register to a selected value identifying that information-representative signal as the first such signal in a digital signal packet.

11. A digital data processing apparatus according to any of claims 1 - 3, wherein said cell interconnect includes means for assembling a digital signal packet including at least one digital information-representative signal representative of a memory address, at least one digital information-representative signal representative of a command, and at least one digital information-representative signal representative of data.

12. A digital data processing apparatus according to claims 1-3, wherein said shift register means includes

A. means for storing a given digital word in a firs stage of said shift register means, and

B. means responsive to said applied digital clock signal for transferring said digital word stored in said first stage to a succeeding stage of said shift register means.

13. A digital data processing apparatus according to claim 12 wherein

a given digital word is resident in said subset of stages associated with said cell interconnect means for (N) applied digital clock cycles.

14. A digital data processing apparatus according to claim 13, wherein said shift register means includes means for simultaneously transferring to successive said stages (p) digital signal packets, where (p) is a positive integer given by

15. A digital data processing apparatus according to claim 13, wherein as the number of stages of said shift register means increases, the flux of said digital words through said stages of said shift register means remains constant.

16. A digital data processing apparatus according to claim 13, wherein clock cycle skew associated with said at least one set of digital clock cycles remains substantially constant with reference to each of said (N) stages of said shift register means as the number (N) increases.

17. A digital data processing apparatus according to any of claims 1 - 3, wherein said cell interconnect means includes at least one of

A. insert buffer means for storing at least a selected digital signal packet for transfer to at least one stage of said associated subset of stages for insertion into said shift register means, and

B. second buffer means for storing at least a selected digital signal packet extracted from said associated subset of stages.

3. A digital data processing apparatus comprising

A. bus means for transferring packets of information-representative digital signals, said bus means including shift register means comprising a plurality of digital storage and transfer stages connected in series in a ring configuration for sequentially storing and transferring said information-representative digital signals, wherein each said stage within said shift register means includes means for storing an information-representative signal of (M) bits, where (M) is greater than one,

B. a plurality of processing cells, connected in a ring configuration through said bus means, each processing cell being in communication with an associated subset of (N) said stages, where (N) is greater than one, at least one of said cells having associated memory means coupled thereto for storing information-representative digital signals,

C. said at least one said processing cell further including cell interconnect means, connected to said associated subset of stages and said associated memory means, for selectively transferring information-representative signals between said associated subset of stages and said associated memory means, and

D. said cell interconnect means including means responsive to applied digital clock cycle signals for simultaneously transferring at least a selected digital signal packet through successive stages of said associated subset of stages, at a rate responsive to said digital clock cycle rate, while performing at least one modifying, extracting, replicating and transferring operation on that same digital signal packet.