GaAs heterostructure metal-insulator-semiconductor integrated circuit technology

• US 5,124,762 A
• Filed: 12/31/1990
• Issued: 06/23/1992
• Est. Priority Date: 12/31/1990
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Nohava, Thomas, Childs, Timothy T.
• Primary Examiner(s): Prenty, Mark
• Assistant Examiner(s): Morin, D.
• Application Number:
  US07/636,321
• Time in Patent Office: 540 Days
• Field of Search: 357/16, 357/23.2, 357/22, 357/91, 357/56
• US Class Current: 257/192
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Heterostructure metal insulator semiconductor integrated circuit technology resulting in, for instance, GaAs field-effect-transistors having much less gate current leakage and greater voltage range than like technology of the related art.

Claims

1. A heterostructure metal insulator semiconductor comprising:

a semi-insulating substrate;

a layer of undoped gallium arsenide on said semi-insulting substrate;

a layer of n doped indium gallium arsenide on said undoped gallium arsenide;

a layer of undoped indium gallium arsenide on said n doped indium gallium arsenide;

a layer of undoped aluminum gallium arsenide on said undoped indium gallium arsenide;

a thin layer of silicon on part of said layer of undoped aluminum gallium arsenide;

a layer of silicon dioxide on said silicon;

a layer of tungsten silicide on said silicon dioxide;

a first portion of said layers of aluminum gallium arsenide, undoped indium gallium arsenide and n doped indium gallium arsenide, having a first ion implant; and

a first ohmic contact on said first implant.

2. Semiconductor of claim 1 further comprising:

a second portion of said layers of aluminum gallium arsenide, undoped indium gallium arsenide, and n doped indium gallium arsenide, having a second ion implant; and

a second ohmic contact on said second implant.

3. Semiconductor of claim 1 further comprising an interface of electron gas between said layer of undoped indium gallium arsenide and said layer of undoped aluminum gallium arsenide.

4. A semiconductor comprising:

a substrate;

a layer of undoped GaAs on said substrate;

a layer of n doped InGaAs on said layer of undoped GaAs;

a layer of undoped InGaAs on said layer of n doped InGaAs;

a layer of undoped AlGaAs on said layer of undoped InGaAs;

a layer of Si on a portion of said layer of undoped AlGaAs;

a layer of SiO₂ on said layer of Si; and

a layer of metal silicide on said layer of SiO₂.

5. Semiconductor of claim 4, further comprising at least one ion implant in said layers of undoped AlGaAs, undoped InGaAs and n doped InGaAs.

6. Semiconductor of claim 5 wherein said layers of metal silicide, SiO₂ and Si form a mesa on said layer of undoped AlGaAs.

7. Semiconductor of claim 6 wherein:

said layer of metal silicide has a thickness between 5 and 10,000 angstroms;

said layer of SiO₂ has a thickness between 75 and 500 angstroms;

said layer of Si has a thickness between 4 and 20 angstroms;

said layer of undoped AlGaAs has a thickness between 25 and 250 angstroms;

said layer of undoped InGaAs has a thickness between 20 and 150 angstroms;

said layer of n doped InGaAs has a thickness between 20 and 150 angstroms; and

said layer of undoped GaAs has a thickness between 0.2 and 1.0 micron.

8. Semiconductor of claim 7 wherein:

the metal of said layer of metal silicide is tungsten; and

said substrate is of semi-insulating GaAs.

9. Semiconductor of claim 8 further comprising an ohmic contact on said layer of undoped AlGaAs in an area of said at least one ion implant.

10. A semiconductor comprising:

a semi-insulating substrate;

a layer of undoped gallium arsenide on said semi-insulating substrate;

a layer of n doped indium gallium arsenide on said undoped gallium arsenide;

a layer of undoped indium gallium arsenide on said n doped indium gallium arsenide;

a layer of undoped aluminum gallium arsenide on said undoped indium gallium arsenide;

a layer of silicon dioxide on a portion of said layer of undoped aluminum gallium arsenide;

a layer of tungsten silicide on said silicon dioxide;

a first portion of said layers of undoped aluminum gallium arsenide, undoped indium gallium arsenide and n doped indium gallium arsenide, having a first ion implant.

11. Semiconductor of claim 10 further comprising:

a second portion of said layers of undoped aluminium gallium arsenide, undoped indium gallium arsenide, and n doped indium gallium arsenide, having a second ion implant;

a first ohmic contact on said first ion implant; and

a second ohmic contact on said second ion implant.

12. Semiconductor of claim 10 further comprising an interface of electron gas between said layer of undoped indium gallium arsenide and said layer of undoped aluminum gallium arsenide.