Computer system speed control at continuous processor speed

• US 5,125,088 A
• Filed: 03/21/1991
• Issued: 06/23/1992
• Est. Priority Date: 09/08/1986
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Culley, Paul R.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): KULIK, PAUL V
• Application Number:
  US07/672,748
• Time in Patent Office: 460 Days
• Field of Search: 364/200, 364/900
• US Class Current: 713/400
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to a speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. In the STOP state the microprocessor (CPU) does not run bus cycles until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computers with older microprocessors. A logic means permits a computer operator to select a speed which the operator wants the microprocessor to "simulate" and also permits the operator to select a type of older microprocessor which the operator wants the new high speed microprocessor to "simulate." A means of automatically varying the apparent microprocessor speed is also disclosed when data transfer from a floppy diskette are detected.

Claims

1. A personal computer with high speed microprocessor compatible with applications software written for slower speed microprocessors comprising:

a bus;

a high speed microprocessor coupled to the bus, having a master clock rate signal input, responsive to a HOLD command for entering a HOLD mode to release control of the bus and to delay commencement of a controlled bus cycle;

a dynamic memory coupled to the bus for storing program instructions and data for use by the personal computer;

a read only memory coupled to the bus for providing program instructions and data to the microprocessor;

a timing device to set a master clock rate for the microprocessor and having an output coupled to the master clock rate input of the microprocessor;

a peripheral device coupled to the bus;

2. The personal computer described in claim 1, wherein the peripheral device is a floppy diskette program storage device and further comprising logic means to monitor the floppy diskette program storage device to provide the HOLD command to place the microprocessor in the HOLD mode wherein execution of microprocessor controlled bus cycles is placed on hold for a selectable length of time, the length of time being provided by the length selection means.

3. The personal computer described in claim 1 wherein the microprocessor is a 32-bit microprocessor.

4. The personal computer described in claim 1 wherein the logic means includes preselected values for different lengths of the HOLD mode to simulate discrete operating speeds of older generation microprocessors.

5. A personal computer system comprising:

a bus;

a microprocessor coupled to the bus, responsive to a HOLD command for entering a HOLD state to release control of the bus and to delay commencement of a controlled bus cycle, operatively coupled to the following;

i) at least one input/output device,

ii) a timing device to set a clock rate of the microprocessor,

iii) a dynamic memory to store data transferred to and from the microprocessor,

iv) means to place said microprocessor in a HOLD state for a preset time interval, said means including;

a DMA subsystem coupled to the bus for transferring data over the bus between the dynamic memory and the input/output device when the microprocessor is in a HOLD state;

means for varying the preset time interval that the execution of bus cycles is in a HOLD state;

means to periodically initiate the execution of the HOLD command for said preset time interval and for allowing the DNA subsystem to gain immediate access to the bus during the time the microprocessor is in the HOLD state; and

means to reinitiate the execution of bus cycles after completion of the HOLD state;

v) a keyboard; and

an operating system,

wherein the preset time interval is a fixed time period and wherein the initiating means is coupled to the input/output device and the preset time interval is initiated by monitoring the input/output device.

6. A personal computer system with varying execution speeds comprising:

a bus;

a microprocessor coupled to the bus, responsive to a HOLD command for entering a HOLD mode to release control of the bus and to delay commencement of a controlled bus cycle, the microprocessor operatively coupled to the following;

i) at least one input/output device,

ii) a timing device to set a matter clock rate of the microprocessor,

iii) a memory device to store data transferred to and from the microprocessor,

iv) means to periodically place said microprocessor in a HOLD mode for a preset time and for selecting the preset time to cause the microprocessor to operate at a simulated reduction in operating speed while the timing device clock rate remains constant and to allow the bus to be inactive for a portion of the preset time,

v) means to re-initiate the execution of bus cycles after completion of the HOLD mode for said preset time, and

vi) a keyboard;

an operating system;

a DMA subsystem coupled to the bus for transferring data over the bus between the dynamic memory and the input/output device when the microprocessor is in a HOLD mode; and

means for allowing the DMA subsystem to be granted access to the bus immediately when the microprocessor is in a HOLD mode upon the initiation of a DMA cycle and the bus is inactive.

7. A personal computer system as set forth in claim 6 wherein the pre-set time is determined by monitoring operation of a floppy diskette drive motor.

8. A personal computer with a high speed microprocessor compatible with applications software written for slower speed microprocessors, the personal computer comprising:

a continuous clock;

a high speed microprocessor coupled to the continuous clock and including a state machine clocked by the continuous clock, the state machine being used to progress the microprocessor through a bus cycle and allowing commands to be processed, the microprocessor responsive to a HOLD command for entering a HOLD mode which halts execution of microprocessor controlled bus cycles and releases control of the bus while continuing operation of the state machine;

a dynamic memory coupled to the bus for storing program instructions and data for use by the personal computer;

a read only memory coupled to the bus for providing program instructions and data to the microprocessor;

means responsive to a mode select signal to periodically provide the HOLD command to place the microprocessor in a HOLD mode, wherein execution of microprocessor controlled bus cycles is placed on hold for a selectable length of time;

a program storage device; and

logic means coupled to said mode select signal responsive means and to the high speed microprocessor for selecting the length of the HOLD mode of the high speed microprocessor to simulate a slower operating speed of said microprocessor.

9. The personal computer described in claim 8, wherein the program storage device is a floppy diskette program storage device and further comprising logic means to monitor the floppy diskette program storage device to provide the HOLD command to place the microprocessor in the HOLD mode for a selected length of time, the length of time being provided by the length select logic means.

10. The personal computer described in claim 8 wherein the microprocessor is a 32-bit microprocessor.

11. The personal computer described in claim 8 wherein the logic means includes preselected values for different lengths of the HOLD mode to simulate discrete operating speeds of older generation microprocessor.

12. A personal computer system comprising:

a continuous clock;

a microprocessor coupled to the continuous clock and including a state machine clocked by the continuous clock, the state machine being used to progress the microprocessor through a bus cycle and allowing commands to be processed, the microprocessor responsive to a HOLD command for entering a HOLD mode which halts execution of microprocessor controlled bus cycles and releases control of the bus while continuing operation of the state machine, operatively coupled to the following;

i) at least one input/output device,

ii) a dynamic memory to store data transfers to and from the microprocessor,

iii) means for periodically providing the HOLD command for a preset time interval to place said microprocessor in a HOLD state, said means including;

means for varying the preset time interval that the execution of bus cycles is in a HOLD state;

means to initiate the execution of the HOLD command for the preset time interval; and

means to re-initiate the execution of bus cycles after completion of the HOLD command;

iv) a keyboard; and

an operating system.

13. The personal computer set forth in claim 12 wherein the preset time interval is a fixed time period and wherein the initiating means is coupled to the input/output device and the preset time interval is initiated by monitoring the input/output device.

14. A personal computer system with varying execution speeds comprising:

a continuous clock;

a microprocessor coupled to the continuous clock and including a state machine clocked by the continuous clock, the state machine being used to progress the microprocessor through a bus cycle and allowing commands to be processed, the microprocessor responsive to a HOLD command for entering a HOLD mode which halts execution of microprocessor controlled bus cycles and releases control of the bus while continuing operation of the state machine, operatively coupled to the following;

i) at least one input/output device,

ii) a memory device to store data transfers to and from the microprocessor,

iii) means to periodically place said microprocessor in a HOLD mode for a preset time,

iv) means to re-initiate the execution of bus cycles by said microprocessor after completion of the HOLD mode for said preset time, and

v) a keyboard,

wherein said preset time is such that the microprocessor operates at a simulated reduction in operating speed while the continuous clock rate remains constant; and

an operating system.

15. A personal computer system as set forth in claim 14 wherein the input/output device is a floppy diskette drive including a motor and the preset time is determined by monitoring operation of the floppy diskette drive motor.

16. A method for operating the microprocessor of a personal computer system at a given clock rate and yet stimulating a slower operating speed and operating in conjunction with a DMA subsystem, the computer system having a bus;

a microprocessor, which is coupled to the bus and is responsive to a HOLD command for entering a HOLD mode wherein control of the bus is released by the microprocessor;

memory coupled to the bus;

a timing device for providing the clock signal to the microprocessor;

a peripheral device coupled to the bus; and

wherein the DMA subsystem is coupled to the bus for transferring data over the bus between the memory and the peripheral device when the microprocessor is in a HOLD mode, the method comprising;

providing the HOLD command to periodically place the microprocessor in the HOLD mode, wherein execution of microprocessor controlled bus cycles is placed on hold for a selectable length of time and to allow the DMA subsystem to gain access to the bus driving the time the microprocessor is in the HOLD mode;

selecting the length of the periodic HOLD mode to simulate a slower operating speed of the microprocessor; and

allowing the DNA subsystem immediate access to the bus during the time the microprocessor is in the HOLD mode.

17. The method of claim 16, wherein the peripheral device is a floppy diskette device and wherein the HOLD command is provided based on monitoring operation of the floppy diskette device.

18. The method of claim 16,

wherein the length of the periodic HOLD mode is selected to simulate discrete operating speeds of older generation microprocessors.

19. The method of claim 16,

wherein the HOLD command is provided based on monitoring operation of the peripheral device.