High speed image processing computer
First Claim
1. An image processing system, comprising:
- an image memory for storing pixel data;
an address generator for generating addresses for accessing said image memory;
a data processor for processing said pixel data associated with said generated addresses;
a mask processor associated with said address generator for generating mask data responsive to said generated addresses; and
a bus connected between said address generator and said data processor for passing mask information therebetween.
3 Assignments
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Accused Products
Abstract
An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). Mask data is generated by a mask processor coupled to the image algorithm processor (66) for masking one or more pixels in a multi-pixel word and further for masking individual bits within said pixels.
148 Citations
17 Claims
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1. An image processing system, comprising:
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an image memory for storing pixel data; an address generator for generating addresses for accessing said image memory; a data processor for processing said pixel data associated with said generated addresses; a mask processor associated with said address generator for generating mask data responsive to said generated addresses; and a bus connected between said address generator and said data processor for passing mask information therebetween. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An image processing system, comprising:
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an image memory for storing pixel data; circuitry for simultaneously writing plural pixels of data in said memory; an address generator for generating addresses for accessing said image memory; a data processor for processing said pixel data associated with said generated addresses; and a mask processor coupled to said address generator for generating mask data responsive to said generated addresses, said mask data operable to prevent desired pixels from being written into said memory during write operations thereto. - View Dependent Claims (12)
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13. A method of processing image data comprising the steps of:
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storing the image data in an image memory; generating addresses for accessing the image memory with an address generator; processing the image data associated with the generated addresses with a data processor; generating mask data responsive to the generated addresses; and passing the mask information between the address generator and the data processor. - View Dependent Claims (14, 15)
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16. The method of processing pixel data comprising the steps of:
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simultaneously writing plural pixels in said memory; generating addresses for accessing the image memory; processing pixel data associated with the generated addresses; generating mask data responsive to said generated addresses; and preventing pixel data associated with the generated mask data from being written into the image memory during write operations thereto. - View Dependent Claims (17)
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Specification