Semiconductor memory device and its fabricating method

• US 5,144,579 A
• Filed: 09/07/1990
• Issued: 09/01/1992
• Est. Priority Date: 09/08/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamada, Takashi, Inoue, Satoshi, Nitayama, Akihiro, Sunouchi, Kazumasa, Takato, Hiroshi, Okabe, Naoko
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/578,608
• Time in Patent Office: 725 Days
• Field of Search: 365/149, 365/180, 365/182, 365/189.01, 365/230.01
• US Class Current: 365/149
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

Claims

1. A semiconductor memory device comprising:

a MOSFET including a gate electrode and source and drain regions of a second electrical conductivity type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity type material;

a bit line connected to one of the source and drain regions of said MOSFET through a bit line contact hole made in an insulating film covering the surface of said substrate on which the MOSFET is formed; and

a capacitor including a storage node electeode formed over a region where said MOSFET is formed, a capacitor insulating film and a plate electrode sequentially formed on said storage node electrode layer to be connected to another of said source and drain regions through a storage node contact hole made in said insulating film,

wherein at least one of said storage node contact hole and bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over said gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive layer embedded in said first contact hole up to a level higher than the gate electrode such as to be contacted with said electrically conductive layer.

2. A semiconductor memory device as set forth in claim 1, wherein both of said storage node contact hole and said bit line contact hole include the first contact hole and the second contact hole, the first contact hole of the storage node contact hole and the first contact hole of the bit line contact hole being made in the same step, the second contact hole of the storage node contact hole and the second contact hole of the bit line contact hole being made in different step.

3. A semiconductor memory device as set forth in claim 1 or 2, wherein said capacitor is formed in a layer higher than said bit line.

4. A semiconductor memory device as set forth in claim 2 or 3, wherein said electrically conductive layer embedded in said storage node contact hole is pextended to an element isolation region, and said second contact hole for contact with the electrically conductive layer is opened over said element isolation region.

5. A semiconductor memory device as set forth in claim 4, wherein said second contact hole corresponding to two of said storage node contact hole each connected to same bit contact hole through said MOSFET are positioned in opposite sides with respect to said bit line and as symmetrical with respect to said bit line contact hole.

6. A semiconductor memory device as set forth in claim 2 or 3, wherein said electrically conductive layer embedded in said bit line contact hole is extended to an element isolation region, and said second contact hole for contact with the electrically conductive layer is opened over said element isolation region.

7. A semiconductor memory device as set forth in any of claims 1 to 5, wherein said electrically conductive layer is grown to have a thickness larger than a depth of said first contact hole and to be expanded over a top of the first contact hole.

8. A semiconductor memory device as set forth in any of claims 1 to 5, wherein said first contact hole is expanded at its top.

9. A semiconductor memory device as set forth in any of claims 1 to 5, wherein said second contact hole is opened larger than said electrically conductive layer at least in one direction.