CMOS winner-take all circuit with offset adaptation

• US 5,146,106 A
• Filed: 02/05/1991
• Issued: 09/08/1992
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Allen, Timothy P., Mead, Carver A., Anderson, Janeen D. W., Wall, Michael F.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): TRAN, TOAN V
• Application Number:
  US07/650,959
• Time in Patent Office: 581 Days
• Field of Search: 307/246, 307/264, 307/482, 307/578, 307/278, 307/350, 307/351, 323/316, 323/317, 330/288, 357/23.5, 365/185
• US Class Current: 327/50
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.

Claims

1. An adaptable circuit, communicating with a plurality of current-carrying lines, for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing, including:

a plurality of MOS current mirrors, each of said current mirrors including an input node, an output node, a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type, the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail, the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor, the gate of said driven MOS current mirror transistor connected to a floating node, a second electrode of said capacitor comprising a portion of said floating node, the drain of said driven MOS current mirror transistor comprising said output node;

a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors, each of said pulldown transistors having its source connected to a second voltage rail, and its gate connected to a common pulldown gate line;

a pulldown gate bias transistor of said second conductivity type, having its source connected to said second voltage rail, its gate connected to a source of bias voltage;

a follower transistor of said second conductivity type associated with each of said current mirrors, having its gate connected to the output of the current mirror with which it is associated, and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line;

means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line, and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit, and for connecting said common pulldown gate line to a source of fixed voltage, and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit; and

means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit;

whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit.

2. The adaptable circuit of claim 1 wherein said means for adjusting the charge on said floating node in response to the output current of said current mirror includes:

electron injecting means coupled to said floating node and responsive to said output current of said current mirror for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said circuit, said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said output current of said current mirror; and

electron removal means coupled to said floating node and responsive to said output current of said current mirror for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said circuit, said electron removal means operating to vary the rate of removal of electrons from said floating node in response to the magnitude of said output current of said current mirror.

3. The adaptable circuit of claim 2 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

4. The adaptable circuit of claim 2 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

5. The adaptable circuit of claim 3 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate,

an n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region, said floating gate electrically connected to said floating node,

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

means for injecting electrons into said p-type region,

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

6. The adaptable circuit of claim 2 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂ .

7. The adaptable circuit of claim 2 wherein said electron injecting means, when enabled, operates to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and wherein said electron removal means operates to increase the rate of removal of electrons from said floating node in response to a decrease in voltage on said floating node.

8. An adaptable circuit, communicating with a plurality of current-carrying lines, for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing, including:

a plurality of MOS current mirrors, each of said current mirrors including an input node, an output node, a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type, the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail, the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor, the gate of said driven MOS current mirror transistor connected to a floating node, a second electrode of said capacitor comprising a portion of said floating node, the drain of said driven MOS current mirror transistor comprising said output node and connected to the gate of said follower transistor;

a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors, each of said pulldown transistors having its source connected to a second voltage rail, and its gate connected to a common pulldown gate line;

a pulldown gate bias transistor of said second conductivity type, having its source connected to said second voltage rail, its gate connected to a source of bias voltage;

a follower transistor of said second conductivity type associated with each of said current mirrors, having its gate connected to the output of the current mirror with which it is associated, and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line;

means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line, and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit, and for connecting said common pulldown gate line to a source of fixed voltage, and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit; and

means for adjusting the charge on said floating node in response to the voltage on said output node during said adapting mode of said circuit;

whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit.

9. The adaptable circuit of claim 8 wherein said means for adjusting the charge on said floating node in response to the output voltage on said output node includes:

electron injecting means coupled to said floating node and responsive to the voltage on said output node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said current mirror, said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said output voltage; and

electron removal means coupled to said floating node and responsive to said output of said current mirror for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, said electron removal means operating to vary the rate of removal of electrons from said floating node in response to the magnitude of said output voltage.

10. The adaptable circuit of claim 9 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

11. The adaptable circuit of claim 9 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

12. The adaptable circuit of claim 10 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate;

a n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region, said floating gate electrically connected to said floating node;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials to act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

13. The adaptable circuit of claim 9 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂ .

14. The adaptable circuit of claim 9 wherein said electron injecting means, when enabled, operates to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and wherein said electron removal means operates to increase the rate of removal of electrons from said floating node in response to a decrease in voltage on said floating node.