Correlator for spread spectrum communications systems

• US 5,146,471 A
• Filed: 04/11/1991
• Issued: 09/08/1992
• Est. Priority Date: 03/23/1989
• Status: Expired due to Term

• Current Assignee: NWF Industries Co.
• Original Assignee: Echelon Systems Corp.
• Inventors: Cowart, Brooks E.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): CAIN, DAVID C
• Application Number:
  US07/684,038
• Time in Patent Office: 516 Days
• Field of Search: 375/1, 380/34
• US Class Current: 375/142
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/70757 with increased resolution, i.e. higher than half a chip H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates

Abstract

An improved correlator for use in a spread spectrum communications system which operates with a predetermined chip sequence includes an N-stage correlation register, wherein each stage corresponds to a signal chip in the sequence, an a means for autocorrelating each of the N stages with the corresponding chips in the sequence. The correlator further includes a means for modifying the sequence to accomodate multiple communication channels.

Claims

1. In a communications system wherein data is recovered by correlating a received spread spectrum signal with a known predetermined chip sequence, an improved correlator comprising:

a correlation register having N stages, where N is an integer greater than zero, with each stage corresponding to a signal chip in said sequence, said correlation register being coupled to receive said spread spectrum signal;

means for autocorrelating each of said N stages with the corresponding chips of said sequence; and

means for modifying said sequence to accommodate multiple communication channels.

2. The improvement of claim 1 wherein said modifying means comprises:

an additional N-stage register receiving code sequence data which defines a weighting value for each of said N-stages of said correlation register; and

logic means for combining the Nth stage of additional register with the Nth stage of said correlation register.

3. The improvement of claim 2 further comprising means for loading said correlation register with the contents of said additional register to allow a selected sequence to be applied to a data stream for subsequent transmission.

4. The improvement of claim 2 wherein said correlation register and said additional register each comprise a linear shift register.

5. The improvement of claim 4 wherein said logic means comprises N 2-input XOR/XNOR logic gates, each gate receiving one of its inputs from said Nth stage of said correlation register and its other input from said Nth stage of said additional register.