MOS dynamic semiconductor memory cell
First Claim
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1. A semiconductor memory comprising:
- a bit line and a word line;
a substrate potential line;
a memory cell including a capacitor element, and a MOS transistor having a drain, a source, a gate, and a back gate, one of said drain and said source being connected to said capacitor element, the other of said drain and said source being connected to said bit line, said gate being connected to said word line, and said back gate being connected to said substrate potential line; and
a potential switching device, connected to said substrate potential line, for selectively switching a potential of said back gate of said MOS transistor.
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Abstract
A semiconductor memory according to the present invention comprises a MOS dynamic semiconductor memory cell in which one terminal of a current path of one MOS transistor is connected to one capacitor element, the other terminal of the current path of the MOS transistor is connected to a bit line, and a gate electrode of the transistor is connected to a word line, wherein a substrate of the MOS transistor is not connected to a fixed potential terminal, and the potential of the substrate is switched and controlled so that the MOS transistor time-selectively becomes an enhancement type or a depletion type which can prevent a threshold voltage loss over time.
78 Citations
11 Claims
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1. A semiconductor memory comprising:
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a bit line and a word line; a substrate potential line; a memory cell including a capacitor element, and a MOS transistor having a drain, a source, a gate, and a back gate, one of said drain and said source being connected to said capacitor element, the other of said drain and said source being connected to said bit line, said gate being connected to said word line, and said back gate being connected to said substrate potential line; and a potential switching device, connected to said substrate potential line, for selectively switching a potential of said back gate of said MOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor memory comprising:
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a bit line and a word line; a substrate potential line; a memory cell including a capacitor element, and a MOS transistor having a drain, a source, a gate, and a back gate, one of said drain and said source being connected to said capacitor element, the other of said drain and said source being connected to said bit line, said gate being connected to said word line, and said back gate being connected to said substrate potential line; and a potential switching device, connected to said substrate potential line, for selectively switching a potential of said back gate of said MOS transistor at predetermined periods of time so that said MOS transistors becomes one of an enhancement type and a depletion type which can prevent threshold voltage loss.
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11. A semiconductor memory comprising:
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a bit line and a word line; a substrate potential line; a memory cell including a capacitor element, and a MOS transistor having a drain, a source, a gate, and a back gate, one of said drain and said source being connected to said capacitor element, the other of said drain and said source being connected to said bit line, said gate being connected to said word line, and said back gate being connected to said substrate potential line; and a potential switching device, connected to said substrate potential line, for selectively switching a potential of said back gate of said MOS transistor at predetermined periods of time so that said MOS transistor becomes one of an enhancement type and a depletion type which can prevent threshold voltage loss, said potential switching device being controlled by timing pulses for selecting said word line.
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Specification