Process for fabricating integrated circuits having shallow junctions

• US 5,149,672 A
• Filed: 08/29/1991
• Issued: 09/22/1992
• Est. Priority Date: 08/01/1988
• Status: Expired due to Term

• Current Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.), Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Schutz, Ronald J., Lifshitz, Nadia
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US07/754,361
• Time in Patent Office: 390 Days
• Field of Search: 437/189, 437/192, 437/190, 437/194, 148/DIG. 20, 148/DIG. 26
• US Class Current: 438/653
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: Y10S 148/02 Contacts, special

Abstract

For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 μm and are made through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completes the contact.

Claims

1. A process for fabricating a semiconductor device comprising the steps of treating a substrate by forming a passage through a region overlying a device junction, depositing a material over at least a portion of said region to form an electrical contact to said junction together with an electrical conducting region on the surface of said overlying region and progressing towards completing said device, characterized in that said passage has an aspect ratio of at least 1.1, said junction has a depth shallower than 2500 Å

, and said electrical contact and said conductive region on said surface comprises a deposition of

     1) a material that presents a barrier to the solid-state diffusion of tungsten and

     2) a deposition of tungsten by interaction of said substrate with a deposition comprising WF₆ entities and a reducing agent wherein said substrate is heated to a deposition temperature in the range 250°

C. to 600°

C. during said tungsten deposition wherein said deposition temperature and environment is controlled such that said interaction is self-limiting with a self-limiting thickness less than said junction depth and wherein said deposition temperature is chosen such that the yield of said junctions decrease not more than 10% compared to the yield obtained for the same function having a via aspect ratio of 0.75 and having a contact of only aluminum.

2. The process of claim 1 wherein said reducing agent comprises hydrogen.

3. The process of claim 2 wherein said diffusion barrier comprises titanium nitride.

4. The process of claim 2 wherein said diffusion barrier comprises a titanium/tungsten alloy.

5. The process of claim 1 wherein said diffusion barrier comprises titanium nitride.

6. The process of claim 1 wherein said diffusion barrier comprises a titanium/tungsten alloy.