Data output driver with substrate biasing producing high output gain

• US 5,157,279 A
• Filed: 07/02/1991
• Issued: 10/20/1992
• Est. Priority Date: 05/28/1991
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seung-Keun
• Primary Examiner(s): Hudspeth, David
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/724,889
• Time in Patent Office: 476 Days
• Field of Search: 307/443, 307/296.2, 307/451
• US Class Current: 326/83
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 5/023 using field effect transistors

Abstract

The data output driver circuit producing high output gain, by controlling the voltage decline caused by body effect produced by a difference between bulk voltage and source voltage in the NMOS transistors connected in series, is disclosed. To obtain such a circuit, the data output driver circuit is provided with a constant voltage means 100 receiving the data from data output buffer and supplying a given voltage to the bulk of first output NMOS transistor 1. Consequently, through the constant voltage circuit 100, the voltage V_cc -V_th equal to the voltage of source of the pull-up transistor 5 is applied to the bulk of the pull-up transistor 5, and in other case, the voltage equal to the voltage between the bulk and the source of the first output transistor 1 is always kept by applying the ground voltage to the bulk of the pull-up transistor. Thus the inventive data output driver has high output gain without the influence caused by body effect. Also the data output driver circuit is applicable to all semiconductor elements and particularly to those semiconductor elements requiring high output gain with potential-low power source voltage.

Claims

1. A data output driver circuit, comprising:

a first output transistor and a second output transistor having a first gate and a second gate, respectively, and receiving an input data signal at said first gate and a complementary data signal at said second gate, said input data signal and said complementary data signal being complementary to each other; and

constant voltage means for supplying a first signal at a first logic level to a bulk of said first output transistor when said input data signal is in a first state, and for supplying said first signal at a second logic level to said bulk of said first output transistor when said input data signal is in a second state;

wherein said constant voltage means comprises;

an input line connected to a gate of said first output transistor;

a pull-up transistor having a gate connected to said input line and having a channel connected in between a first potential terminal and said bulk of said first output resistor; and

a pull-down transistor having a gate connected to said input line and having a channel connected in between said bulk of said first output transistor and a second potential terminal.

2. The data output driver circuit, as claimed in claim 1, further comprising bias means connected in between said input line and a second potential terminal, for supplying a bias voltage to said input line when a potential of said input line is lower than a predetermined level.

5. The data output driver circuit, according to claim 1, wherein a channel of said first output transistor is connected between said first potential and a data output node, and a channel of said second output transistor is connected between said data output node and said second potential.

6. The data output driver circuit, according to claim 5, wherein a bulk of said second output transistor is connected to said second potential.

7. The data output driver circuit, according to claim 1, further comprising an inverter means for inverting said data signal received by said pull-down transistor.

8. The data output driver circuit, according to claim 1, further comprising a second potential terminal connected to a bulk of said pull-down transistor and a bulk of said pull-up transistor.

9. The data output driver circuit as claimed in claim 2, wherein said bias means comprises a first potential terminal, a second potential terminal, and a bias stage transistor having a gate connected to said first potential terminal and a channel of said bias stage transistor connected between said input line and said second potential.

11. The data output driver circuit, as claimed in claim 1, wherein the second potential is a ground potential.

3. A data output driver circuit, comprising:

a first output transistor and a second output transistor having a first gate connected to a first input line and a second gate connected to a second input line, respectively, to receive an input data signal at said first gate and a complementary data signal at said second gate, wherein said input data signal and said complementary data signal are complementary;

a pull-up transistor having a gate connected to said first input line and having a channel connected in between a source potential terminal and a bulk of said first output transistor;

a pull-down transistor having a gate connected to one of said first input line and said second input line and having a channel connected in between said bulk of said first output transistor and a ground potential terminal; and

bias means connected in between said first input line and a ground potential terminal, for supplying a bias voltage to said first input line when a potential of said first input line is lower than a given level.

4. The data output driver as claimed in claim 3, wherein said bias means discharges the potential of said first input line to said ground potential when the potential of said first input line is lower than approximately 2.4V.

10. A data output driver circuit, comprising:

a first output transistor and a second output transistor having a first gate and a second gate, respectively, and means for receiving a digital data signal at said first gate and a complementary data signal at said second gate, said digital data signal and said complementary data signal being complementary to each other; and

constant voltage means for supplying an output signal exhibiting a logic low state to a bulk of said first output transistor when said digital data signal is in a logic low state, and for supplying said output signal exhibiting state a logic high state to said bulk of said first output transistor when said digital data signal is in a logic high state.