Circuits for linear conversion between currents and voltages
First Claim
Patent Images
1. A current negator circuit, including:
- an input section including;
an input node for a current to be mirrored,a first voltage rail connected to a source of a first electrical potential,a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential,a first P-channel MOS transistor, having its gate connected to said input node, its drain connected to said input node, and its source connected to said first voltage rail,a first N-channel MOS transistor, having its gate connected to said input node, its drain connected to said input node, and its source connected to said second voltage rail,at least one output section, said at least one output section including;
an output node,a third voltage rail connected to a source of a third electrical potential,a fourth voltage rail connected to a source of a fourth electrical potential more negative than said third electrical potential,a second P-channel MOS transistor, having its gate connected to said input node, its drain connected to said output node, and its source connected to said third voltage rail,a second N-channel MOS transistor, having its gate connected to said input node, its drain connected to said output node, and its source connected to said fourth voltage rail.
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Abstract
A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.
124 Citations
6 Claims
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1. A current negator circuit, including:
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an input section including; an input node for a current to be mirrored, a first voltage rail connected to a source of a first electrical potential, a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential, a first P-channel MOS transistor, having its gate connected to said input node, its drain connected to said input node, and its source connected to said first voltage rail, a first N-channel MOS transistor, having its gate connected to said input node, its drain connected to said input node, and its source connected to said second voltage rail, at least one output section, said at least one output section including; an output node, a third voltage rail connected to a source of a third electrical potential, a fourth voltage rail connected to a source of a fourth electrical potential more negative than said third electrical potential, a second P-channel MOS transistor, having its gate connected to said input node, its drain connected to said output node, and its source connected to said third voltage rail, a second N-channel MOS transistor, having its gate connected to said input node, its drain connected to said output node, and its source connected to said fourth voltage rail.
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2. A current negator circuit, including:
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an input section including; an input node for a current to be mirrored, a first voltage rail connected to a source of a first electrical potential, a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential, a first P-channel MOS transistor, having its source connected to said first voltage rail and its drain connected to said input node, a first N-channel MOS transistor, having its source connected to said second voltage rail and its drain connected to said input node, at least one output section, said at least one output section including; an output node, a second P-channel MOS transistor, having its gate and drain connected to the gate of said first P-channel MOS transistor and its source connected to said third voltage rail, a third P-channel MOS transistor, having its gate connected to said input node, its source connected to the drain of said second P-channel MOS transistor, and its drain connected to said output node, a third voltage rail connected to a source of a third electrical potential, a fourth voltage rail connected to a source of a fourth electrical potential more negative than said first electrical potential, a second N-channel MOS transistor, having its gate and drain connected to the gate of said first N-channel MOS transistor and its source connected to said fourth voltage rail, a third N-channel MOS transistor, having its gate connected to said input node, its source connected to the drain of said second N-channel MOS transistor, and its drain connected to said output node.
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3. A current negator circuit, including:
an input section including; an input node for a current to be mirrored, a first voltage rail connected to a source of a first electrical potential, a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential, a first P-channel MOS transistor, having its gate connected to its drain and its source connected to said first voltage rail, a second P-channel MOS transistor, having its source connected to the drain of said first P-channel MOS transistor and its source connected to said input node, a first N-channel MOS transistor, having its gate connected to its drain and its source connected to said second voltage rail, a second N-channel MOS transistor, having its source connected to the drain of said first N-channel MOS transistor and its drain connected to said input node, at least one output section, said at least one output section including; an output node, a third voltage rail connected to a source of a third electrical potential, a fourth voltage rail connected to a source of a fourth electrical potential more negative than said first electrical potential, a third P-channel MOS transistor, having its source connected to said third voltage rail, and its gate connected to the gate of said first P-channel MOS transistor, a fourth P-channel MOS transistor, having its gate connected to said input node, its source connected to the drain of said third P-channel MOS transistor, and its drain connected to said output node, a third N-channel MOS transistor, having its source connected to said fourth voltage rail, its gate connected to the gate of said first N-channel MOS transistor, and its drain connected to the gate of said second N-channel MOS transistor, a fourth N-channel MOS transistor, having its gate connected to said input node, its source connected to the drain of said third N-channel MOS transistor, and its drain connected to said output node.
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4. A current negator circuit, including:
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an input section including; an input node for a current to be mirrored, a first voltage rail connected to a source of a first electrical potential, a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential, a first P-channel MOS transistor, having its gate connected to its drain and its source connected to said first voltage rail, a second P-channel MOS transistor, having its gate and drain connected to said input node, and its source connected to the drain of said first P-channel MOS transistor, a first N-channel MOS transistor, having its gate connected to its drain and its source connected to said second voltage rail, a second N-channel MOS transistor, having its gate and drain connected to said input node and its source connected to the drain of said first N-channel MOS transistor, at least one output section, said at least one output section including; an output node, a third voltage rail connected to a source of a third electrical potential, a fourth voltage rail connected to a source of a fourth electrical potential more negative than said third electrical potential, a third P-channel MOS transistor, having its gate connected to the gate of said first P-channel MOS transistor and its source connected to said third voltage rail, a fourth P-channel MOS transistor, having its gate connected to the gate of said second P-channel MOS transistor, its drain connected to said output node and its source connected to the drain of said third P-channel MOS transistor, a third N-channel MOS transistor, having its gate connected to the gate of said first N-channel MOS transistor and its source connected to said fourth voltage rail, a fourth P-channel MOS transistor, having its gate connected to the gate of said second N-channel MOS transistor, its drain connected to said output node and its source connected to the drain of said third N-channel MOS transistor.
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5. A current negator circuit, including:
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an input section including; an input node for a current to be mirrored, a first voltage rail connected to a source of a first electrical potential, a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential, a first P-channel MOS transistor, having its gate connected to its drain and its source connected to said first voltage rail, a second P-channel MOS transistor, having its gate connected to its drain and its source connected to the drain of said first P-channel MOS transistor, a third P-channel MOS transistor, having its gate and drain and to said input node, and its source connected to the drain of said second P-channel MOS transistor, a first N-channel MOS transistor, having its gate connected to its drain and its source connected to said second voltage rail, a second N-channel MOS transistor, having its gate connected to its drain and its source connected to the drain of said first N-channel MOS transistor, a third N-channel MOS transistor, having its gate and drain and to said input node, and its source connected to the drain of said second N-channel MOS transistor, at least one output section, said at least one output section including; an output node, a third voltage rail connected to a source of a third electrical potential, a fourth voltage rail connected to a source of a fourth electrical potential more negative than said third electrical potential, a fourth P-channel MOS transistor, having its gate connected to the gate of said first P-channel MOS transistor, and its source connected to said third voltage rail, a fifth P-channel MOS transistor, having its gate connected to the gate of said second P-channel MOS transistor, and its source connected to the drain of said fourth P-channel MOS transistor, a sixth P-channel MOS transistor, having its gate connected to the gate of said third P-channel MOS transistor, its source connected to the drain of said fifth P-channel MOS transistor, and its drain connected to said output node, a fourth N-channel MOS transistor, having its gate connected to the gate of said first N-channel MOS transistor, and its source connected to said fourth voltage rail, a fifth N-channel MOS transistor, having its gate connected to the gate of said second N-channel MOS transistor, and its source connected to the drain of said fourth N-channel MOS transistor, a sixth N-channel MOS transistor, having its gate connected to the gate of said third N-channel MOS transistor, its source connected to the drain of said fifth N-channel MOS transistor, and its drain connected to said output node.
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6. A non-inverting linear voltage-to-current converter circuit, including:
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an input node for an input voltage, an output node for an output current, an intermediate node, a first voltage rail connected to a source of a first electrical potential, a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential, a first P-channel MOS transistor, having its gate connected to said input node, its drain connected to said intermediate node, and its source connected to said first voltage rail, a first N-channel MOS transistor, having its gate connected to said input node, its drain connected to said intermediate node, and its source connected to said second voltage rail, the voltages on said first and second voltage rails chosen to be greater than the sum of the magnitudes of the threshold voltages of said first P-channel MOS transistor and said first N-channel MOS transistor and the sizes of said first P-channel MOS transistor and said first N-channel MOS transistor being chosen such that the quadratic dependance of the current through said first P-channel MOS transistor balances the quadratic dependance of the current through said first N-channel MOS transistor and both said first P-channel MOS transistor and said first N-channel MOS transistor being operated above threshold and in saturation, a third voltage rail connected to a source of a third electrical potential, a fourth voltage rail connected to a source of a second electrical potential more negative than said third electrical potential, a second P-channel MOS transistor, having its gate and drain connected to said intermediate node, and its source connected to said third voltage rail, a second N-channel MOS transistor, having its gate and drain connected to said intermediate node, and its source connected to said fourth voltage rail, the voltages on said third and fourth voltage rails chosen to be greater than the sum of the magnitudes of the threshold voltages of said second P-channel MOS transistor and said second N-channel MOS transistor and the sizes of said second P-channel MOS transistor and said second N-channel MOS transistor being chosen such that the quadratic dependance of the current through said second P-channel MOS transistor balances the quadratic dependance of the current through said second N-channel MOS transistor and both said second P-channel MOS transistor and said second N-channel MOS transistor being operated above threshold and in saturation, a fifth voltage rail connected to a source of a fifth electrical potential, a sixth voltage rail connected to a source of a sixth electrical potential more negative than said fifth electrical potential, a third P-channel MOS transistor, having its gate connected to said intermediate node, its drain connected to said output node, and its source connected to said fifth voltage rail, a third N-channel MOS transistor, having its gate connected to said intermediate node, its drain connected to said output node, and its source connected to said sixth voltage rail, the voltages on said fifth and sixth voltage rails chosen to be greater than the sum of the magnitudes of the threshold voltages of said third P-channel MOS transistor and said third N-channel MOS transistor and the sizes of said third P-channel MOS transistor and said third N-channel MOS transistor being chosen such that the quadratic dependance of the current through said third P-channel MOS transistor balances the quadratic dependance of the current through said third N-channel MOS transistor and both said third P-channel MOS transistor and said third N-channel MOS transistor being operated above threshold and in saturation.
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Specification
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Current AssigneeSynaptics Incorporated
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Original AssigneeSynaptics Incorporated
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InventorsPlatt, John C., Mead, Carver A., Wall, Michael F., Gribble, Glenn E.
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Primary Examiner(s)MOTTOLA, STEVEN J
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Application NumberUS07/629,470Time in Patent Office700 DaysField of Search307/292, 307/501, 307/502, 323/315, 323/316, 330/277, 330/288, 330/310, 330/264US Class Current330/277CPC Class CodesH03F 2203/30006 the push and the pull stage...H03F 2203/30009 the push and pull stages of...H03F 2203/30084 the pull circuit of the SEP...H03F 2203/30117 the push circuit of the SEP...H03F 3/3001 with field-effect transistorsH03F 3/3022 CMOS common source output S...
