Semiconductor memory

  • US 5,170,374 A
  • Filed: 04/07/1992
  • Issued: 12/08/1992
  • Est. Priority Date: 05/13/1981
  • Status: Expired due to Term
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First Claim
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1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

  • a pair of data lines disposed substantially parallel and adjacent to each other;

    a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

    a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof;

    an amplifier coupled to said pair of data lines for amplifying a potential difference with exists between said data lines, said amplifier comprising first and second circuits;

    wherein said circuit includes a first MISFET of a first conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a second MISFET of said first conductivity type having its drain coupled to said gate of said first MISFET, its gate coupled to said drain of said first MISFET and its source coupled to a source of said first MISFET, a third MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with a first power source voltage and its gate supplied with a first timing signal, and a fourth MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with said first power source voltage and its gate supplied with a second timing signal; and

    wherein said second circuit includes a fifth MISFET of a second conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a sixth MISFET of said second conductivity type having its drain coupled to said gate of said fifth MISFET, its gate coupled to said drain of said fifth MISFET and its source coupled to a source of said fifth MISFET, and a seventh MISFET of said second conductivity type having its drain coupled to said source of said fifth MISFET, its source supplied with a second power source voltage and its gate supplied with a third timing signal,wherein said third MISFET is turned "on" in response to said first timing signal at a time different from a time when said fourth MISFET is turned "on" in response to said second timing signals, and wherein said seventh MISFET is turned "on" in response to said third timing signal at a time different from said time when said fourth MISFET is turned "on" in response to said second timing signals.

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